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Only avoid the check if we're the last operand before the variable

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operands in a variadic instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119446 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2010-11-17 00:55:36 +00:00
parent 6bc105a7b9
commit 113a06cff4
1 changed files with 3 additions and 3 deletions
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6
lib/CodeGen/MachineVerifier.cpp
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@ -558,9 +558,9 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
else if (MO->isImplicit())
report("Explicit definition marked as implicit", MO, MONum);
} else if (MONum < TI.getNumOperands()) {
// Don't check if it's a variadic instruction. See, e.g., LDM_RET in the arm
// back end.
if (MO->isReg() && MONum != TI.getNumOperands()-1) {
// Don't check if it's the last operand in a variadic instruction. See,
// e.g., LDM_RET in the arm back end.
if (MO->isReg() && !(TI.isVariadic() && MONum == TI.getNumOperands()-1)) {
if (MO->isDef())
report("Explicit operand marked as def", MO, MONum);
if (MO->isImplicit())