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Generate Neon VTBL and VTBX instructions from the corresponding intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78835 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
parent
a6340628c2
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114a266c94
@ -1989,6 +1989,59 @@ def VZIPq8 : N2VQShuffle<0b00, 0b00011, "vzip.8">;
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def VZIPq16 : N2VQShuffle<0b01, 0b00011, "vzip.16">;
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def VZIPq32 : N2VQShuffle<0b10, 0b00011, "vzip.32">;
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// Vector Table Lookup and Table Extension.
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// VTBL : Vector Table Lookup
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def VTBL1
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: N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
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(ins DPR:$tbl1, DPR:$src), NoItinerary,
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"vtbl.8\t$dst, \\{$tbl1\\}, $src", "",
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[(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
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def VTBL2
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: N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
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(ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NoItinerary,
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"vtbl.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "",
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[(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
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DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
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def VTBL3
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: N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
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(ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NoItinerary,
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"vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "",
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[(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
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DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
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def VTBL4
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: N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
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(ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NoItinerary,
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"vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "",
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[(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
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DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
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// VTBX : Vector Table Extension
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def VTBX1
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: N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
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(ins DPR:$orig, DPR:$tbl1, DPR:$src), NoItinerary,
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"vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst",
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[(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
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DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
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def VTBX2
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: N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
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(ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NoItinerary,
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"vtbx.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst",
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[(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
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DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
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def VTBX3
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: N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
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(ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NoItinerary,
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"vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst",
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[(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
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DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
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def VTBX4
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: N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
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DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NoItinerary,
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"vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst",
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[(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
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DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
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//===----------------------------------------------------------------------===//
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// NEON instructions for single-precision FP math
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//===----------------------------------------------------------------------===//
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@ -83,6 +83,36 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd,
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FirstOpnd = 3;
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NumRegs = 4;
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return true;
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case ARM::VTBL2:
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FirstOpnd = 1;
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NumRegs = 2;
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return true;
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case ARM::VTBL3:
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FirstOpnd = 1;
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NumRegs = 3;
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return true;
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case ARM::VTBL4:
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FirstOpnd = 1;
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NumRegs = 4;
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return true;
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case ARM::VTBX2:
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FirstOpnd = 2;
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NumRegs = 2;
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return true;
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case ARM::VTBX3:
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FirstOpnd = 2;
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NumRegs = 3;
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return true;
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case ARM::VTBX4:
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FirstOpnd = 2;
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NumRegs = 4;
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return true;
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}
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return false;
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109
test/CodeGen/ARM/vtbl.ll
Normal file
109
test/CodeGen/ARM/vtbl.ll
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@ -0,0 +1,109 @@
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; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
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%struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
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%struct.__builtin_neon_v8qi3 = type { <8 x i8>, <8 x i8>, <8 x i8> }
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%struct.__builtin_neon_v8qi4 = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
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define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vtbl1:
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;CHECK: vtbl.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <8 x i8> @llvm.arm.neon.vtbl1(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__builtin_neon_v8qi2* %B) nounwind {
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;CHECK: vtbl2:
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;CHECK: vtbl.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__builtin_neon_v8qi2* %B
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%tmp3 = extractvalue %struct.__builtin_neon_v8qi2 %tmp2, 0
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%tmp4 = extractvalue %struct.__builtin_neon_v8qi2 %tmp2, 1
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%tmp5 = call <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4)
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ret <8 x i8> %tmp5
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}
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define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__builtin_neon_v8qi3* %B) nounwind {
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;CHECK: vtbl3:
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;CHECK: vtbl.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__builtin_neon_v8qi3* %B
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%tmp3 = extractvalue %struct.__builtin_neon_v8qi3 %tmp2, 0
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%tmp4 = extractvalue %struct.__builtin_neon_v8qi3 %tmp2, 1
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%tmp5 = extractvalue %struct.__builtin_neon_v8qi3 %tmp2, 2
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%tmp6 = call <8 x i8> @llvm.arm.neon.vtbl3(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5)
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ret <8 x i8> %tmp6
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}
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define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__builtin_neon_v8qi4* %B) nounwind {
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;CHECK: vtbl4:
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;CHECK: vtbl.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__builtin_neon_v8qi4* %B
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%tmp3 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 0
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%tmp4 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 1
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%tmp5 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 2
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%tmp6 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 3
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%tmp7 = call <8 x i8> @llvm.arm.neon.vtbl4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6)
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ret <8 x i8> %tmp7
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}
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define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
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;CHECK: vtbx1:
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;CHECK: vtbx.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = load <8 x i8>* %C
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%tmp4 = call <8 x i8> @llvm.arm.neon.vtbx1(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
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ret <8 x i8> %tmp4
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}
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define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__builtin_neon_v8qi2* %B, <8 x i8>* %C) nounwind {
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;CHECK: vtbx2:
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;CHECK: vtbx.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__builtin_neon_v8qi2* %B
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%tmp3 = extractvalue %struct.__builtin_neon_v8qi2 %tmp2, 0
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%tmp4 = extractvalue %struct.__builtin_neon_v8qi2 %tmp2, 1
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%tmp5 = load <8 x i8>* %C
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%tmp6 = call <8 x i8> @llvm.arm.neon.vtbx2(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5)
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ret <8 x i8> %tmp6
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}
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define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__builtin_neon_v8qi3* %B, <8 x i8>* %C) nounwind {
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;CHECK: vtbx3:
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;CHECK: vtbx.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__builtin_neon_v8qi3* %B
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%tmp3 = extractvalue %struct.__builtin_neon_v8qi3 %tmp2, 0
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%tmp4 = extractvalue %struct.__builtin_neon_v8qi3 %tmp2, 1
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%tmp5 = extractvalue %struct.__builtin_neon_v8qi3 %tmp2, 2
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%tmp6 = load <8 x i8>* %C
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%tmp7 = call <8 x i8> @llvm.arm.neon.vtbx3(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6)
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ret <8 x i8> %tmp7
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}
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define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__builtin_neon_v8qi4* %B, <8 x i8>* %C) nounwind {
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;CHECK: vtbx4:
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;CHECK: vtbx.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__builtin_neon_v8qi4* %B
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%tmp3 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 0
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%tmp4 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 1
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%tmp5 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 2
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%tmp6 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 3
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%tmp7 = load <8 x i8>* %C
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%tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7)
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ret <8 x i8> %tmp8
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}
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declare <8 x i8> @llvm.arm.neon.vtbl1(<8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbl3(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbl4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbx1(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbx2(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbx3(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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