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Bug fix. Not advancing the register scavenger iterator correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35020 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -42,7 +42,6 @@ namespace {
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const MRegisterInfo *MRI;
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const MRegisterInfo *MRI;
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ARMFunctionInfo *AFI;
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ARMFunctionInfo *AFI;
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RegScavenger *RS;
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RegScavenger *RS;
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MachineBasicBlock::iterator RSI;
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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@ -67,6 +66,7 @@ namespace {
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int Opcode, unsigned Size, unsigned Scratch,
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int Opcode, unsigned Size, unsigned Scratch,
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MemOpQueue &MemOps);
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MemOpQueue &MemOps);
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void AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps);
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bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
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bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
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bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
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bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
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};
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};
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@ -492,6 +492,22 @@ static bool isMemoryOp(MachineInstr *MI) {
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return false;
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return false;
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}
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}
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/// AdvanceRS - Advance register scavenger to just before the earliest memory
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/// op that is being merged.
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void ARMLoadStoreOpt::AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps) {
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MachineBasicBlock::iterator Loc = MemOps[0].MBBI;
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unsigned Position = MemOps[0].Position;
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for (unsigned i = 1, e = MemOps.size(); i != e; ++i) {
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if (MemOps[i].Position < Position) {
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Position = MemOps[i].Position;
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Loc = MemOps[i].MBBI;
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}
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}
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if (Loc != MBB.begin())
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RS->forward(prior(Loc));
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}
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/// LoadStoreMultipleOpti - An optimization pass to turn multiple LDR / STR
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/// LoadStoreMultipleOpti - An optimization pass to turn multiple LDR / STR
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/// ops of the same base and incrementing offset into LDM / STM ops.
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/// ops of the same base and incrementing offset into LDM / STM ops.
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bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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@ -504,7 +520,6 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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unsigned Position = 0;
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unsigned Position = 0;
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RS->enterBasicBlock(&MBB);
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RS->enterBasicBlock(&MBB);
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RSI = MBB.begin();
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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while (MBBI != E) {
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bool Advance = false;
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bool Advance = false;
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@ -585,15 +600,14 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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if (TryMerge) {
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if (TryMerge) {
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if (NumMemOps > 1) {
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if (NumMemOps > 1) {
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// Try to find a free register to use as a new base in case it's needed.
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// Try to find a free register to use as a new base in case it's needed.
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unsigned Scratch = ARM::R12;
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// First advance to the instruction just before the start of the chain.
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// First advance to the instruction just before the start of the chain.
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if (RSI != MBB.begin())
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AdvanceRS(MBB, MemOps);
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RS->forward(prior(RSI));
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// Find a scratch register. Make sure it's a call clobbered register or
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// Find a scratch register. Make sure it's a call clobbered register or
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// a spilled callee-saved register.
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// a spilled callee-saved register.
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Scratch = RS->FindUnusedReg(&ARM::GPRRegClass, true);
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unsigned Scratch = RS->FindUnusedReg(&ARM::GPRRegClass, true);
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if (!Scratch)
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if (!Scratch)
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RS->FindUnusedReg(&ARM::GPRRegClass, AFI->getSpilledCSRegisters());
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Scratch = RS->FindUnusedReg(&ARM::GPRRegClass,
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AFI->getSpilledCSRegisters());
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// Process the load / store instructions.
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// Process the load / store instructions.
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RS->forward(prior(MBBI));
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RS->forward(prior(MBBI));
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@ -617,7 +631,6 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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// RS may be pointing to an instruction that's deleted.
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// RS may be pointing to an instruction that's deleted.
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RS->skipTo(prior(MBBI));
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RS->skipTo(prior(MBBI));
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RSI = MBBI;
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}
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}
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CurrBase = 0;
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CurrBase = 0;
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