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[AArch64][FastISel] Fix integer extend optimization.
The integer extend optimization tries to fold the extend into the load instruction. This requires us to identify if the extend has already been emitted or not and act accordingly on it. The check that was originally performed for this was not sufficient. Besides checking the ValueMap for a mapped register we also need to check if the virtual register has already an associated machine instruction that defines it. This fixes rdar://problem/20470788. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234529 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1917,7 +1917,8 @@ bool AArch64FastISel::selectLoad(const Instruction *I) {
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// could select it. Emit a copy to subreg if necessary. FastISel will remove
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// it when it selects the integer extend.
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unsigned Reg = lookUpRegForValue(IntExtVal);
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if (!Reg) {
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auto *MI = MRI.getUniqueVRegDef(Reg);
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if (!MI) {
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if (RetVT == MVT::i64 && VT <= MVT::i32) {
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if (WantZExt) {
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// Delete the last emitted instruction from emitLoad (SUBREG_TO_REG).
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@ -1935,10 +1936,7 @@ bool AArch64FastISel::selectLoad(const Instruction *I) {
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// The integer extend has already been emitted - delete all the instructions
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// that have been emitted by the integer extend lowering code and use the
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// result from the load instruction directly.
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while (Reg) {
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auto *MI = MRI.getUniqueVRegDef(Reg);
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if (!MI)
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break;
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while (MI) {
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Reg = 0;
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for (auto &Opnd : MI->uses()) {
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if (Opnd.isReg()) {
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@ -1947,6 +1945,9 @@ bool AArch64FastISel::selectLoad(const Instruction *I) {
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}
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}
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MI->eraseFromParent();
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MI = nullptr;
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if (Reg)
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MI = MRI.getUniqueVRegDef(Reg);
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}
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updateValueMap(IntExtVal, ResultReg);
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return true;
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19
test/CodeGen/AArch64/fast-isel-int-ext5.ll
Normal file
19
test/CodeGen/AArch64/fast-isel-int-ext5.ll
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@ -0,0 +1,19 @@
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; RUN: llc -mtriple=aarch64-apple-darwin -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: int_ext_opt
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define i64 @int_ext_opt(i8* %addr, i1 %c1, i1 %c2) {
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entry:
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%0 = load i8, i8* %addr
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br i1 %c1, label %bb1, label %bb2
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bb1:
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%1 = zext i8 %0 to i64
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br i1 %c2, label %bb2, label %exit
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bb2:
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%2 = phi i64 [1, %entry], [%1, %bb1]
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ret i64 %2
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exit:
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ret i64 0
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}
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