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Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled.
rdar://problem/9276427 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129456 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1470,7 +1470,8 @@ static bool DisassembleThumb2DPSoReg(MCInst &MI, unsigned Opcode, uint32_t insn,
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static bool DisassembleThumb2DPModImm(MCInst &MI, unsigned Opcode,
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uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
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const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
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const TargetInstrDesc &TID = ARMInsts[Opcode];
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const TargetOperandInfo *OpInfo = TID.OpInfo;
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unsigned &OpIdx = NumOpsAdded;
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OpIdx = 0;
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@ -1497,8 +1498,15 @@ static bool DisassembleThumb2DPModImm(MCInst &MI, unsigned Opcode,
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DEBUG(errs()<<"Thumb2 encoding error: d==15 for DPModImm 2-reg instr.\n");
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return false;
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}
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RnRegClassID,
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decodeRn(insn))));
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int Idx;
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if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
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// The reg operand is tied to the first reg operand.
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MI.addOperand(MI.getOperand(Idx));
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} else {
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// Add second reg operand.
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RnRegClassID,
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decodeRn(insn))));
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}
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++OpIdx;
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}
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@ -241,3 +241,6 @@
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# CHECK: rfedb lr
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0x1e 0xe8 0x00 0xc0
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# CHECK: mov.w r3, #4294967295
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0x4f 0xf0 0xff 0x33
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