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Add a register class -> virtual registers map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57844 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -33,6 +33,11 @@ class MachineRegisterInfo {
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/// start of the use/def list for the register.
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std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo;
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/// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to
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/// virtual registers. For each target register class, it keeps a list of
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/// virtual registers belonging to the class.
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std::vector<std::vector<unsigned> > RegClass2VRegMap;
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/// PhysRegUseDefLists - This is an array of the head of the use/def list for
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/// physical registers.
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MachineOperand **PhysRegUseDefLists;
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@ -130,6 +135,7 @@ public:
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//===--------------------------------------------------------------------===//
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/// getRegClass - Return the register class of the specified virtual register.
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///
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const TargetRegisterClass *getRegClass(unsigned Reg) const {
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Reg -= TargetRegisterInfo::FirstVirtualRegister;
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assert(Reg < VRegInfo.size() && "Invalid vreg!");
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@ -137,10 +143,22 @@ public:
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}
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/// setRegClass - Set the register class of the specified virtual register.
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///
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void setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
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unsigned VR = Reg;
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Reg -= TargetRegisterInfo::FirstVirtualRegister;
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assert(Reg < VRegInfo.size() && "Invalid vreg!");
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const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
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VRegInfo[Reg].first = RC;
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// Remove from old register class's vregs list. This may be slow but
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// fortunately this operation is rarely needed.
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std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
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std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR);
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VRegs.erase(I);
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// Add to new register class's vregs list.
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RegClass2VRegMap[RC->getID()].push_back(VR);
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}
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/// createVirtualRegister - Create and return a new virtual register in the
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@ -152,12 +170,12 @@ public:
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void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
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VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
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if (&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)
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return getLastVirtReg();
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// Otherwise, the vector reallocated, handle this now.
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if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)))
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// The vector reallocated, handle this now.
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HandleVRegListReallocation();
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return getLastVirtReg();
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unsigned VR = getLastVirtReg();
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RegClass2VRegMap[RegClass->getID()].push_back(VR);
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return VR;
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}
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/// getLastVirtReg - Return the highest currently assigned virtual register.
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@ -166,6 +184,11 @@ public:
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return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1;
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}
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/// getRegClassVirtRegs - Return the list of virtual registers of the given
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/// target register class.
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std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) {
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return RegClass2VRegMap[RC->getID()];
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}
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//===--------------------------------------------------------------------===//
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// Physical Register Use Info
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@ -16,6 +16,7 @@ using namespace llvm;
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MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
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VRegInfo.reserve(256);
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RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1.
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UsedPhysRegs.resize(TRI.getNumRegs());
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// Create the physreg use/def lists.
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