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PPC: Add support for fctid and fctiw

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Encodings were checked against the Power ISA documents and double
checked against binutils.

This fixes PR17350.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191419 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Majnemer 2013-09-26 04:11:24 +00:00
parent 9fa81ab838
commit 11c2b15c0a
4 changed files with 20 additions and 8 deletions
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8
lib/Target/PowerPC/PPCISelLowering.h
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@ -42,10 +42,10 @@ namespace llvm {
/// unsigned integers and single-precision outputs.
FCFIDU, FCFIDS, FCFIDUS,
/// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
/// operand, producing an f64 value containing the integer representation
/// of that FP value.
FCTIDZ, FCTIWZ,
/// FCTI[D,W]Z? - The FCTID, FCTIDZ, FCTIW and FCTIWZ instructions,
/// taking an f32 or f64 operand, producing an f64 value containing the
/// integer representation of that FP value.
FCTID, FCTIDZ, FCTIW, FCTIWZ,
/// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
/// unsigned integers.

3
lib/Target/PowerPC/PPCInstr64Bit.td
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@ -968,6 +968,9 @@ let PPC970_Unit = 3, neverHasSideEffects = 1,
defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
"fcfid", "$frD, $frB", FPGeneral,
[(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
"fctid", "$frD, $frB", FPGeneral,
[(set f64:$frD, (PPCfctid f64:$frB))]>, isPPC64;
defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
"fctidz", "$frD, $frB", FPGeneral,
[(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;

5
lib/Target/PowerPC/PPCInstrInfo.td
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@ -69,7 +69,9 @@ def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
def PPCfctid : SDNode<"PPCISD::FCTID", SDTFPUnaryOp, []>;
def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
def PPCfctiw : SDNode<"PPCISD::FCTIW", SDTFPUnaryOp, []>;
def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
@ -1692,6 +1694,9 @@ let isCompare = 1, neverHasSideEffects = 1 in {
let Uses = [RM] in {
let neverHasSideEffects = 1 in {
defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
"fctiw", "$frD, $frB", FPGeneral,
[(set f64:$frD, (PPCfctiw f64:$frB))]>;
defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
"fctiwz", "$frD, $frB", FPGeneral,
[(set f64:$frD, (PPCfctiwz f64:$frB))]>;

12
test/MC/PowerPC/ppc64-encoding-fp.s
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@ -173,8 +173,10 @@
# CHECK: frsp. 2, 3 # encoding: [0xfc,0x40,0x18,0x19]
frsp. 2, 3
# FIXME: fctid 2, 3
# FIXME: fctid. 2, 3
# CHECK: fctid 2, 3 # encoding: [0xfc,0x40,0x1e,0x5c]
fctid 2, 3
# CHECK: fctid. 2, 3 # encoding: [0xfc,0x40,0x1e,0x5d]
fctid. 2, 3
# CHECK: fctidz 2, 3 # encoding: [0xfc,0x40,0x1e,0x5e]
fctidz 2, 3
# CHECK: fctidz. 2, 3 # encoding: [0xfc,0x40,0x1e,0x5f]
@ -185,8 +187,10 @@
fctiduz 2, 3
# CHECK: fctiduz. 2, 3 # encoding: [0xfc,0x40,0x1f,0x5f]
fctiduz. 2, 3
# FIXME: fctiw 2, 3
# FIXME: fctiw. 2, 3
# CHECK: fctiw 2, 3 # encoding: [0xfc,0x40,0x18,0x1c]
fctiw 2, 3
# CHECK: fctiw. 2, 3 # encoding: [0xfc,0x40,0x18,0x1d]
fctiw. 2, 3
# CHECK: fctiwz 2, 3 # encoding: [0xfc,0x40,0x18,0x1e]
fctiwz 2, 3
# CHECK: fctiwz. 2, 3 # encoding: [0xfc,0x40,0x18,0x1f]