6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00
Code Issues Projects Releases Wiki Activity

[X86] Add a temporary testcase for PR21876/r223996.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224074 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ahmed Bougacha 2014-12-11 23:07:52 +00:00
parent e39dba9f07
commit 11fcb48306
2 changed files with 30 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/Target/X86/X86InstrSSE.td
View File

@ -6178,6 +6178,7 @@ multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, SDNode ExtOp> {
(!cast<I>(OpcPrefix#DQYrr) VR128:$src)>;
// On AVX2, we also support 256bit inputs.
// FIXME: remove these patterns when the old shuffle lowering goes away.
def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
(!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),

29
test/CodeGen/X86/avx2-pmovx-256-old-shuffle.ll Normal file
View File

@ -0,0 +1,29 @@
; RUN: llc < %s -x86-experimental-vector-shuffle-lowering=false -mattr=+avx2 | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-darwin"
; PR21876
; The old shuffle lowering sometimes generates VZEXT nodes with both input
; and output same-sized types, here 256-bits. For instance, a v8i8 to v8i32
; zero-extend would become a (v8i32 (VZEXT v32i8)) node, which can't happen
; otherwise. The companion commit r223996 added those patterns temporarily.
; This test, along with the VR256 for AVX2 PMOVXrr instructions, should be
; removed once the old vector shuffle lowering goes away.
define void @test_avx2_pmovx_256(<8 x i8>* %tmp64, <8 x float>* %tmp75) {
; CHECK-LABEL: test_avx2_pmovx_256
; We really don't care about the generated code.
; CHECK: vpmovzxbd
; CHECK: vpbroadcastd
; CHECK: vpand
; CHECK: vcvtdq2ps
; CHECK: vmovups
; CHECK: vzeroupper
; CHECK: retq
%wide.load458 = load <8 x i8>* %tmp64, align 1
%tmp68 = uitofp <8 x i8> %wide.load458 to <8 x float>
store <8 x float> %tmp68, <8 x float>* %tmp75, align 4
ret void
}