6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-19 06:31:18 +00:00
Code Issues Projects Releases Wiki Activity

Reformatting of lines. Put multiple DEBUG statements under one DEBUG statement.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78411 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2009-08-07 21:33:25 +00:00
parent d77c7aba83
commit 1232167ce3
1 changed files with 78 additions and 45 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

123
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -107,23 +107,37 @@ namespace {
} }
void dump() { void dump() {
cerr << "X86ISelAddressMode " << this << "\n"; cerr << "X86ISelAddressMode " << this << '\n';
cerr << "Base.Reg "; cerr << "Base.Reg ";
if (Base.Reg.getNode() != 0) Base.Reg.getNode()->dump(); if (Base.Reg.getNode() != 0)
else cerr << "nul"; Base.Reg.getNode()->dump();
cerr << " Base.FrameIndex " << Base.FrameIndex << "\n"; else
cerr << " Scale" << Scale << "\n"; cerr << "nul";
cerr << " Base.FrameIndex " << Base.FrameIndex << '\n';
cerr << " Scale" << Scale << '\n';
cerr << "IndexReg "; cerr << "IndexReg ";
if (IndexReg.getNode() != 0) IndexReg.getNode()->dump(); if (IndexReg.getNode() != 0)
else cerr << "nul"; IndexReg.getNode()->dump();
cerr << " Disp " << Disp << "\n"; else
cerr << "GV "; if (GV) GV->dump(); cerr << "nul";
else cerr << "nul"; cerr << " Disp " << Disp << '\n';
cerr << " CP "; if (CP) CP->dump(); cerr << "GV ";
else cerr << "nul"; if (GV)
cerr << "\n"; GV->dump();
cerr << "ES "; if (ES) cerr << ES; else cerr << "nul"; else
cerr << " JT" << JT << " Align" << Align << "\n"; cerr << "nul";
cerr << " CP ";
if (CP)
CP->dump();
else
cerr << "nul";
cerr << '\n';
cerr << "ES ";
if (ES)
cerr << ES;
else
cerr << "nul";
cerr << " JT" << JT << " Align" << Align << '\n';
} }
}; };
} }
@ -806,7 +820,10 @@ bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
unsigned Depth) { unsigned Depth) {
bool is64Bit = Subtarget->is64Bit(); bool is64Bit = Subtarget->is64Bit();
DebugLoc dl = N.getDebugLoc(); DebugLoc dl = N.getDebugLoc();
DEBUG(errs() << "MatchAddress: "); DEBUG(AM.dump()); DEBUG({
errs() << "MatchAddress: ";
AM.dump();
});
// Limit recursion. // Limit recursion.
if (Depth > 5) if (Depth > 5)
return MatchAddressBase(N, AM); return MatchAddressBase(N, AM);
@ -1593,17 +1610,21 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
DebugLoc dl = Node->getDebugLoc(); DebugLoc dl = Node->getDebugLoc();
#ifndef NDEBUG #ifndef NDEBUG
DEBUG(errs() << std::string(Indent, ' ') << "Selecting: "); DEBUG({
DEBUG(Node->dump(CurDAG)); errs() << std::string(Indent, ' ') << "Selecting: ";
DEBUG(errs() << "\n"); Node->dump(CurDAG);
errs() << '\n';
});
Indent += 2; Indent += 2;
#endif #endif
if (Node->isMachineOpcode()) { if (Node->isMachineOpcode()) {
#ifndef NDEBUG #ifndef NDEBUG
DEBUG(errs() << std::string(Indent-2, ' ') << "== "); DEBUG({
DEBUG(Node->dump(CurDAG)); errs() << std::string(Indent-2, ' ') << "== ";
DEBUG(errs() << "\n"); Node->dump(CurDAG);
errs() << '\n';
});
Indent -= 2; Indent -= 2;
#endif #endif
return NULL; // Already selected. return NULL; // Already selected.
@ -1642,7 +1663,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
SDValue N1 = Node->getOperand(1); SDValue N1 = Node->getOperand(1);
bool isSigned = Opcode == ISD::SMUL_LOHI; bool isSigned = Opcode == ISD::SMUL_LOHI;
if (!isSigned) if (!isSigned) {
switch (NVT.getSimpleVT()) { switch (NVT.getSimpleVT()) {
default: llvm_unreachable("Unsupported VT!"); default: llvm_unreachable("Unsupported VT!");
case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break; case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
@ -1650,7 +1671,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break; case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break; case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
} }
else } else {
switch (NVT.getSimpleVT()) { switch (NVT.getSimpleVT()) {
default: llvm_unreachable("Unsupported VT!"); default: llvm_unreachable("Unsupported VT!");
case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break; case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
@ -1658,6 +1679,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break; case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break; case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
} }
}
unsigned LoReg, HiReg; unsigned LoReg, HiReg;
switch (NVT.getSimpleVT()) { switch (NVT.getSimpleVT()) {
@ -1670,7 +1692,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
// multiplty is commmutative // Multiply is commmutative.
if (!foldedLoad) { if (!foldedLoad) {
foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
if (foldedLoad) if (foldedLoad)
@ -1701,9 +1723,11 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
InFlag = Result.getValue(2); InFlag = Result.getValue(2);
ReplaceUses(N.getValue(0), Result); ReplaceUses(N.getValue(0), Result);
#ifndef NDEBUG #ifndef NDEBUG
DEBUG(errs() << std::string(Indent-2, ' ') << "=> "); DEBUG({
DEBUG(Result.getNode()->dump(CurDAG)); errs() << std::string(Indent-2, ' ') << "=> ";
DEBUG(errs() << "\n"); Result.getNode()->dump(CurDAG);
errs() << '\n';
});
#endif #endif
} }
// Copy the high half of the result, if it is needed. // Copy the high half of the result, if it is needed.
@ -1729,9 +1753,11 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
} }
ReplaceUses(N.getValue(1), Result); ReplaceUses(N.getValue(1), Result);
#ifndef NDEBUG #ifndef NDEBUG
DEBUG(errs() << std::string(Indent-2, ' ') << "=> "); DEBUG({
DEBUG(Result.getNode()->dump(CurDAG)); errs() << std::string(Indent-2, ' ') << "=> ";
DEBUG(errs() << "\n"); Result.getNode()->dump(CurDAG);
errs() << '\n';
});
#endif #endif
} }
@ -1748,7 +1774,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
SDValue N1 = Node->getOperand(1); SDValue N1 = Node->getOperand(1);
bool isSigned = Opcode == ISD::SDIVREM; bool isSigned = Opcode == ISD::SDIVREM;
if (!isSigned) if (!isSigned) {
switch (NVT.getSimpleVT()) { switch (NVT.getSimpleVT()) {
default: llvm_unreachable("Unsupported VT!"); default: llvm_unreachable("Unsupported VT!");
case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break; case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
@ -1756,7 +1782,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break; case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break; case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
} }
else } else {
switch (NVT.getSimpleVT()) { switch (NVT.getSimpleVT()) {
default: llvm_unreachable("Unsupported VT!"); default: llvm_unreachable("Unsupported VT!");
case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break; case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
@ -1764,6 +1790,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break; case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break; case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
} }
}
unsigned LoReg, HiReg; unsigned LoReg, HiReg;
unsigned ClrOpcode, SExtOpcode; unsigned ClrOpcode, SExtOpcode;
@ -1871,9 +1898,11 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
InFlag = Result.getValue(2); InFlag = Result.getValue(2);
ReplaceUses(N.getValue(0), Result); ReplaceUses(N.getValue(0), Result);
#ifndef NDEBUG #ifndef NDEBUG
DEBUG(errs() << std::string(Indent-2, ' ') << "=> "); DEBUG({
DEBUG(Result.getNode()->dump(CurDAG)); errs() << std::string(Indent-2, ' ') << "=> ";
DEBUG(errs() << "\n"); Result.getNode()->dump(CurDAG);
errs() << '\n';
});
#endif #endif
} }
// Copy the remainder (high) result, if it is needed. // Copy the remainder (high) result, if it is needed.
@ -1900,9 +1929,11 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
} }
ReplaceUses(N.getValue(1), Result); ReplaceUses(N.getValue(1), Result);
#ifndef NDEBUG #ifndef NDEBUG
DEBUG(errs() << std::string(Indent-2, ' ') << "=> "); DEBUG({
DEBUG(Result.getNode()->dump(CurDAG)); errs() << std::string(Indent-2, ' ') << "=> ";
DEBUG(errs() << "\n"); Result.getNode()->dump(CurDAG);
errs() << '\n';
});
#endif #endif
} }
@ -1958,12 +1989,14 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
SDNode *ResNode = SelectCode(N); SDNode *ResNode = SelectCode(N);
#ifndef NDEBUG #ifndef NDEBUG
DEBUG(errs() << std::string(Indent-2, ' ') << "=> "); DEBUG({
if (ResNode == NULL || ResNode == N.getNode()) errs() << std::string(Indent-2, ' ') << "=> ";
DEBUG(N.getNode()->dump(CurDAG)); if (ResNode == NULL || ResNode == N.getNode())
else N.getNode()->dump(CurDAG);
DEBUG(ResNode->dump(CurDAG)); else
DEBUG(errs() << "\n"); ResNode->dump(CurDAG);
errs() << '\n';
});
Indent -= 2; Indent -= 2;
#endif #endif