mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
R600: Add support for SET*_DX10 instructions
These instructions compare two floating point values and return an integer true (-1) or false (0) value. When compiling code generated by the Mesa GLSL frontend, the SET*_DX10 instructions save us four instructions for most branch decisions that use floating-point comparisons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174609 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
2a77cf7f47
commit
1234c9be42
@ -90,7 +90,9 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
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setTargetDAGCombine(ISD::FP_ROUND);
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setTargetDAGCombine(ISD::FP_TO_SINT);
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setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
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setTargetDAGCombine(ISD::SELECT_CC);
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setSchedulingPreference(Sched::VLIW);
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}
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@ -670,9 +672,12 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
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}
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// Try to lower to a SET* instruction:
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// We need all the operands of SELECT_CC to have the same value type, so if
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// necessary we need to change True and False to be the same type as LHS and
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// RHS, and then convert the result of the select_cc back to the correct type.
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//
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// CompareVT == MVT::f32 and VT == MVT::i32 is supported by the hardware,
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// but for the other case where CompareVT != VT, all operands of
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// SELECT_CC need to have the same value type, so we need to change True and
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// False to be the same type as LHS and RHS, and then convert the result of
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// the select_cc back to the correct type.
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// Move hardware True/False values to the correct operand.
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if (isHWTrueValue(False) && isHWFalseValue(True)) {
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@ -682,32 +687,17 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
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}
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if (isHWTrueValue(True) && isHWFalseValue(False)) {
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if (CompareVT != VT) {
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if (VT == MVT::f32 && CompareVT == MVT::i32) {
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SDValue Boolean = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
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LHS, RHS,
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DAG.getConstant(-1, MVT::i32),
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DAG.getConstant(0, MVT::i32),
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CC);
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// Convert integer values of true (-1) and false (0) to fp values of
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// true (1.0f) and false (0.0f).
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SDValue LSB = DAG.getNode(ISD::AND, DL, MVT::i32, Boolean,
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DAG.getConstant(1, MVT::i32));
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return DAG.getNode(ISD::UINT_TO_FP, DL, VT, LSB);
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} else if (VT == MVT::i32 && CompareVT == MVT::f32) {
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SDValue BoolAsFlt = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
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LHS, RHS,
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DAG.getConstantFP(1.0f, MVT::f32),
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DAG.getConstantFP(0.0f, MVT::f32),
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CC);
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// Convert fp values of true (1.0f) and false (0.0f) to integer values
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// of true (-1) and false (0).
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SDValue Neg = DAG.getNode(ISD::FNEG, DL, MVT::f32, BoolAsFlt);
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return DAG.getNode(ISD::FP_TO_SINT, DL, VT, Neg);
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} else {
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// I don't think there will be any other type pairings.
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assert(!"Unhandled operand type parings in SELECT_CC");
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}
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if (CompareVT != VT && VT == MVT::f32 && CompareVT == MVT::i32) {
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SDValue Boolean = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
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LHS, RHS,
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DAG.getConstant(-1, MVT::i32),
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DAG.getConstant(0, MVT::i32),
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CC);
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// Convert integer values of true (-1) and false (0) to fp values of
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// true (1.0f) and false (0.0f).
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SDValue LSB = DAG.getNode(ISD::AND, DL, MVT::i32, Boolean,
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DAG.getConstant(1, MVT::i32));
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return DAG.getNode(ISD::UINT_TO_FP, DL, VT, LSB);
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} else {
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// This SELECT_CC is already legal.
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return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
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@ -1128,6 +1118,35 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
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}
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break;
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}
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// (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
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// (i32 select_cc f32, f32, -1, 0 cc)
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//
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// Mesa's GLSL frontend generates the above pattern a lot and we can lower
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// this to one of the SET*_DX10 instructions.
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case ISD::FP_TO_SINT: {
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SDValue FNeg = N->getOperand(0);
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if (FNeg.getOpcode() != ISD::FNEG) {
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return SDValue();
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}
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SDValue SelectCC = FNeg.getOperand(0);
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if (SelectCC.getOpcode() != ISD::SELECT_CC ||
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SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
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SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
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!isHWTrueValue(SelectCC.getOperand(2)) ||
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!isHWFalseValue(SelectCC.getOperand(3))) {
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return SDValue();
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}
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return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N->getValueType(0),
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SelectCC.getOperand(0), // LHS
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SelectCC.getOperand(1), // RHS
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DAG.getConstant(-1, MVT::i32), // True
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DAG.getConstant(0, MVT::i32), // Flase
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SelectCC.getOperand(4)); // CC
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break;
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}
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// Extract_vec (Build_vector) generated by custom lowering
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// also needs to be customly combined
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case ISD::EXTRACT_VECTOR_ELT: {
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@ -1147,6 +1166,37 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
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}
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}
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}
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case ISD::SELECT_CC: {
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// fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
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// selectcc x, y, a, b, inv(cc)
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SDValue LHS = N->getOperand(0);
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if (LHS.getOpcode() != ISD::SELECT_CC) {
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return SDValue();
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}
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SDValue RHS = N->getOperand(1);
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SDValue True = N->getOperand(2);
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SDValue False = N->getOperand(3);
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if (LHS.getOperand(2).getNode() != True.getNode() ||
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LHS.getOperand(3).getNode() != False.getNode() ||
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RHS.getNode() != False.getNode() ||
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cast<CondCodeSDNode>(N->getOperand(4))->get() != ISD::SETEQ) {
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return SDValue();
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}
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ISD::CondCode CCOpcode = cast<CondCodeSDNode>(LHS->getOperand(4))->get();
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CCOpcode = ISD::getSetCCInverse(
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CCOpcode, LHS.getOperand(0).getValueType().isInteger());
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return DAG.getSelectCC(N->getDebugLoc(),
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LHS.getOperand(0),
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LHS.getOperand(1),
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LHS.getOperand(2),
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LHS.getOperand(3),
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CCOpcode);
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}
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}
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return SDValue();
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}
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@ -711,6 +711,34 @@ def SNE : R600_2OP <
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COND_NE))]
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>;
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def SETE_DX10 : R600_2OP <
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0xC, "SETE_DX10",
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[(set R600_Reg32:$dst,
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(selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
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COND_EQ))]
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>;
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def SETGT_DX10 : R600_2OP <
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0xD, "SETGT_DX10",
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[(set R600_Reg32:$dst,
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(selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
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COND_GT))]
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>;
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def SETGE_DX10 : R600_2OP <
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0xE, "SETGE_DX10",
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[(set R600_Reg32:$dst,
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(selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
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COND_GE))]
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>;
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def SETNE_DX10 : R600_2OP <
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0xF, "SETNE_DX10",
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[(set R600_Reg32:$dst,
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(selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
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COND_NE))]
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>;
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def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;
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def TRUNC : R600_1OP_Helper <0x11, "TRUNC", int_AMDGPU_trunc>;
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def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
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@ -1772,6 +1800,18 @@ def : Pat <
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(SGE R600_Reg32:$src1, R600_Reg32:$src0)
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>;
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// SETGT_DX10 reverse args
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def : Pat <
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(selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, COND_LT),
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(SETGT_DX10 R600_Reg32:$src1, R600_Reg32:$src0)
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>;
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// SETGE_DX10 reverse args
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def : Pat <
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(selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, COND_LE),
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(SETGE_DX10 R600_Reg32:$src1, R600_Reg32:$src0)
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>;
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// SETGT_INT reverse args
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def : Pat <
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(selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
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@ -1810,12 +1850,24 @@ def : Pat <
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(SETE R600_Reg32:$src0, R600_Reg32:$src1)
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>;
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//SETE_DX10 - 'true if ordered'
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def : Pat <
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(selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETO),
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(SETE_DX10 R600_Reg32:$src0, R600_Reg32:$src1)
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>;
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//SNE - 'true if unordered'
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def : Pat <
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(selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO),
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(SNE R600_Reg32:$src0, R600_Reg32:$src1)
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>;
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//SETNE_DX10 - 'true if ordered'
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def : Pat <
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(selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUO),
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(SETNE_DX10 R600_Reg32:$src0, R600_Reg32:$src1)
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>;
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def : Extract_Element <f32, v4f32, R600_Reg128, 0, sel_x>;
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def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>;
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def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>;
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@ -1,8 +1,6 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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;CHECK: SETE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;CHECK: MOV T{{[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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;CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;CHECK: SETE_DX10 T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @test(i32 addrspace(1)* %out, float addrspace(1)* %in) {
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entry:
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137
test/CodeGen/R600/set-dx10.ll
Normal file
137
test/CodeGen/R600/set-dx10.ll
Normal file
@ -0,0 +1,137 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; These tests check that floating point comparisons which are used by select
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; to store integer true (-1) and false (0) values are lowered to one of the
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; SET*DX10 instructions.
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; CHECK: @fcmp_une_select_fptosi
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; CHECK: SETNE_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00)
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define void @fcmp_une_select_fptosi(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp une float %in, 5.0
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%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
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%2 = fsub float -0.000000e+00, %1
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%3 = fptosi float %2 to i32
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: @fcmp_une_select_i32
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; CHECK: SETNE_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00)
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define void @fcmp_une_select_i32(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp une float %in, 5.0
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%1 = select i1 %0, i32 -1, i32 0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: @fcmp_ueq_select_fptosi
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; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00)
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define void @fcmp_ueq_select_fptosi(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp ueq float %in, 5.0
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%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
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%2 = fsub float -0.000000e+00, %1
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%3 = fptosi float %2 to i32
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: @fcmp_ueq_select_i32
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; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00)
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define void @fcmp_ueq_select_i32(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp ueq float %in, 5.0
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%1 = select i1 %0, i32 -1, i32 0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: @fcmp_ugt_select_fptosi
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; CHECK: SETGT_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00)
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define void @fcmp_ugt_select_fptosi(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp ugt float %in, 5.0
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%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
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%2 = fsub float -0.000000e+00, %1
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%3 = fptosi float %2 to i32
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: @fcmp_ugt_select_i32
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; CHECK: SETGT_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00)
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define void @fcmp_ugt_select_i32(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp ugt float %in, 5.0
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%1 = select i1 %0, i32 -1, i32 0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: @fcmp_uge_select_fptosi
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; CHECK: SETGE_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00)
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define void @fcmp_uge_select_fptosi(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp uge float %in, 5.0
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%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
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%2 = fsub float -0.000000e+00, %1
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%3 = fptosi float %2 to i32
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: @fcmp_uge_select_i32
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; CHECK: SETGE_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00)
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define void @fcmp_uge_select_i32(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp uge float %in, 5.0
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%1 = select i1 %0, i32 -1, i32 0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: @fcmp_ule_select_fptosi
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; CHECK: SETGE_DX10 T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00)
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define void @fcmp_ule_select_fptosi(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp ule float %in, 5.0
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%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
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%2 = fsub float -0.000000e+00, %1
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%3 = fptosi float %2 to i32
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: @fcmp_ule_select_i32
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; CHECK: SETGE_DX10 T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00)
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define void @fcmp_ule_select_i32(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp ule float %in, 5.0
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%1 = select i1 %0, i32 -1, i32 0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; CHECK: @fcmp_ult_select_fptosi
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; CHECK: SETGT_DX10 T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00)
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define void @fcmp_ult_select_fptosi(i32 addrspace(1)* %out, float %in) {
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entry:
|
||||
%0 = fcmp ult float %in, 5.0
|
||||
%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
|
||||
%2 = fsub float -0.000000e+00, %1
|
||||
%3 = fptosi float %2 to i32
|
||||
store i32 %3, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: @fcmp_ult_select_i32
|
||||
; CHECK: SETGT_DX10 T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00)
|
||||
define void @fcmp_ult_select_i32(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
%0 = fcmp ult float %in, 5.0
|
||||
%1 = select i1 %0, i32 -1, i32 0
|
||||
store i32 %1, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
@ -24,21 +24,21 @@ entry:
|
||||
|
||||
; CHECK: @ult_float
|
||||
; CHECK: SETGT T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00)
|
||||
define void @ult_float(i32 addrspace(1)* %out, float %in) {
|
||||
define void @ult_float(float addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
%0 = fcmp ult float %in, 5.0
|
||||
%1 = select i1 %0, i32 -1, i32 0
|
||||
store i32 %1, i32 addrspace(1)* %out
|
||||
%1 = select i1 %0, float 1.0, float 0.0
|
||||
store float %1, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: @olt
|
||||
; CHECK: SETGT T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00)
|
||||
define void @olt(i32 addrspace(1)* %out, float %in) {
|
||||
define void @olt(float addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
%0 = fcmp olt float %in, 5.0
|
||||
%1 = select i1 %0, i32 -1, i32 0
|
||||
store i32 %1, i32 addrspace(1)* %out
|
||||
%1 = select i1 %0, float 1.0, float 0.0
|
||||
store float %1, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -64,20 +64,20 @@ entry:
|
||||
|
||||
; CHECK: @ule_float
|
||||
; CHECK: SETGE T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00)
|
||||
define void @ule_float(i32 addrspace(1)* %out, float %in) {
|
||||
define void @ule_float(float addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
%0 = fcmp ule float %in, 5.0
|
||||
%1 = select i1 %0, i32 -1, i32 0
|
||||
store i32 %1, i32 addrspace(1)* %out
|
||||
%1 = select i1 %0, float 1.0, float 0.0
|
||||
store float %1, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: @ole
|
||||
; CHECK: SETGE T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00)
|
||||
define void @ole(i32 addrspace(1)* %out, float %in) {
|
||||
define void @ole(float addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
%0 = fcmp ole float %in, 5.0
|
||||
%1 = select i1 %0, i32 -1, i32 0
|
||||
store i32 %1, i32 addrspace(1)* %out
|
||||
%1 = select i1 %0, float 1.0, float 0.0
|
||||
store float %1, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user