mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-26 07:34:06 +00:00
Initial support for addrmode handling. Tests by Brian Lucas!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86382 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
603fce9ebb
commit
123ed8f099
@ -295,22 +295,23 @@ void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum,
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const MachineOperand &Base = MI->getOperand(OpNum);
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const MachineOperand &Disp = MI->getOperand(OpNum+1);
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if (Base.isGlobal())
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printOperand(MI, OpNum, "mem");
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else if (Disp.isImm() && !Base.getReg())
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// Print displacement first
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if (!Disp.isImm()) {
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printOperand(MI, OpNum+1, "mem");
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} else {
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if (!Base.getReg())
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O << '&';
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printOperand(MI, OpNum+1, "nohash");
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}
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// Print register base field
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if (Base.getReg()) {
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O << '(';
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printOperand(MI, OpNum);
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else if (Base.getReg()) {
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if (Disp.getImm()) {
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printOperand(MI, OpNum + 1, "nohash");
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O << '(';
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printOperand(MI, OpNum);
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O << ')';
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} else {
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O << '@';
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printOperand(MI, OpNum);
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}
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} else
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llvm_unreachable("Unsupported memory operand");
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O << ')';
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}
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}
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void MSP430AsmPrinter::printCCOperand(const MachineInstr *MI, int OpNum) {
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@ -63,25 +63,22 @@ void MSP430InstPrinter::printSrcMemOperand(const MCInst *MI, unsigned OpNo,
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const MCOperand &Base = MI->getOperand(OpNo);
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const MCOperand &Disp = MI->getOperand(OpNo+1);
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// FIXME: move global to displacement field!
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if (Base.isExpr()) {
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// Print displacement first
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if (Disp.isExpr()) {
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O << '&';
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Base.getExpr()->print(O, &MAI);
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} else if (Disp.isImm() && !Base.isReg())
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printOperand(MI, OpNo);
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else if (Base.isReg()) {
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if (Disp.getImm()) {
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O << Disp.getImm() << '(';
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printOperand(MI, OpNo);
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O << ')';
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} else {
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O << '@';
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printOperand(MI, OpNo);
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}
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Disp.getExpr()->print(O, &MAI);
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} else {
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Base.dump();
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Disp.dump();
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llvm_unreachable("Unsupported memory operand");
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assert(Disp.isImm() && "Expected immediate in displacement field");
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if (!Base.getReg())
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O << '&';
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O << Disp.getImm();
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}
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// Print register base field
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if (Base.getReg()) {
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O << '(' << getRegisterName(Base.getReg()) << ')';
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}
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}
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@ -45,6 +45,70 @@ static const bool ViewRMWDAGs = false;
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STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
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namespace {
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struct MSP430ISelAddressMode {
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enum {
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RegBase,
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FrameIndexBase
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} BaseType;
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struct { // This is really a union, discriminated by BaseType!
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SDValue Reg;
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int FrameIndex;
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} Base;
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int16_t Disp;
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GlobalValue *GV;
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Constant *CP;
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BlockAddress *BlockAddr;
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const char *ES;
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int JT;
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unsigned Align; // CP alignment.
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MSP430ISelAddressMode()
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: BaseType(RegBase), Disp(0), GV(0), CP(0), BlockAddr(0),
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ES(0), JT(-1), Align(0) {
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}
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bool hasSymbolicDisplacement() const {
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return GV != 0 || CP != 0 || ES != 0 || JT != -1;
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}
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bool hasBaseReg() const {
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return Base.Reg.getNode() != 0;
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}
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void setBaseReg(SDValue Reg) {
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BaseType = RegBase;
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Base.Reg = Reg;
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}
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void dump() {
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errs() << "MSP430ISelAddressMode " << this << '\n';
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if (Base.Reg.getNode() != 0) {
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errs() << "Base.Reg ";
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Base.Reg.getNode()->dump();
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} else {
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errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
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}
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errs() << " Disp " << Disp << '\n';
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if (GV) {
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errs() << "GV ";
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GV->dump();
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} else if (CP) {
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errs() << " CP ";
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CP->dump();
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errs() << " Align" << Align << '\n';
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} else if (ES) {
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errs() << "ES ";
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errs() << ES << '\n';
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} else if (JT != -1)
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errs() << " JT" << JT << " Align" << Align << '\n';
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}
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};
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}
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/// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
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/// instructions for SelectionDAG operations.
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///
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@ -65,6 +129,10 @@ namespace {
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return "MSP430 DAG->DAG Pattern Instruction Selection";
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}
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bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
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bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
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bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
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bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
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SDNode *Root) const;
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@ -95,50 +163,155 @@ FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
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return new MSP430DAGToDAGISel(TM, OptLevel);
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}
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// FIXME: This is pretty dummy routine and needs to be rewritten in the future.
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bool MSP430DAGToDAGISel::SelectAddr(SDValue Op, SDValue Addr,
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SDValue &Base, SDValue &Disp) {
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// Try to match frame address first.
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i16);
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Disp = CurDAG->getTargetConstant(0, MVT::i16);
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/// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode.
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/// These wrap things that will resolve down into a symbol reference. If no
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/// match is possible, this returns true, otherwise it returns false.
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bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) {
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// If the addressing mode already has a symbol as the displacement, we can
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// never match another symbol.
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if (AM.hasSymbolicDisplacement())
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return true;
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SDValue N0 = N.getOperand(0);
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
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AM.GV = G->getGlobal();
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AM.Disp += G->getOffset();
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//AM.SymbolFlags = G->getTargetFlags();
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} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
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AM.CP = CP->getConstVal();
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AM.Align = CP->getAlignment();
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AM.Disp += CP->getOffset();
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//AM.SymbolFlags = CP->getTargetFlags();
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} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
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AM.ES = S->getSymbol();
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//AM.SymbolFlags = S->getTargetFlags();
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} else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
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AM.JT = J->getIndex();
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//AM.SymbolFlags = J->getTargetFlags();
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} else {
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AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
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//AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
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}
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return false;
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}
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/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
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/// specified addressing mode without any further recursion.
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bool MSP430DAGToDAGISel::MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) {
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// Is the base register already occupied?
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if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
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// If so, we cannot select it.
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return true;
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}
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switch (Addr.getOpcode()) {
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case ISD::ADD:
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// Operand is a result from ADD with constant operand which fits into i16.
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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uint64_t CVal = CN->getZExtValue();
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// Offset should fit into 16 bits.
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if (((CVal << 48) >> 48) == CVal) {
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SDValue N0 = Addr.getOperand(0);
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N0))
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i16);
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else
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Base = N0;
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// Default, generate it as a register.
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AM.BaseType = MSP430ISelAddressMode::RegBase;
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AM.Base.Reg = N;
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return false;
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}
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bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) {
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DebugLoc dl = N.getDebugLoc();
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DEBUG({
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errs() << "MatchAddress: ";
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AM.dump();
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});
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switch (N.getOpcode()) {
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default: break;
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case ISD::Constant: {
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uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
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AM.Disp += Val;
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return false;
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}
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Disp = CurDAG->getTargetConstant(CVal, MVT::i16);
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return true;
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}
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}
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break;
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case MSP430ISD::Wrapper:
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SDValue N0 = Addr.getOperand(0);
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
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Base = CurDAG->getTargetGlobalAddress(G->getGlobal(),
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MVT::i16, G->getOffset());
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Disp = CurDAG->getTargetConstant(0, MVT::i16);
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return true;
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} else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(N0)) {
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Base = CurDAG->getTargetExternalSymbol(E->getSymbol(), MVT::i16);
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Disp = CurDAG->getTargetConstant(0, MVT::i16);
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if (!MatchWrapper(N, AM))
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return false;
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break;
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case ISD::FrameIndex:
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if (AM.BaseType == MSP430ISelAddressMode::RegBase
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&& AM.Base.Reg.getNode() == 0) {
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AM.BaseType = MSP430ISelAddressMode::FrameIndexBase;
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AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
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return false;
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}
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break;
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};
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Base = Addr;
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Disp = CurDAG->getTargetConstant(0, MVT::i16);
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case ISD::ADD: {
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MSP430ISelAddressMode Backup = AM;
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if (!MatchAddress(N.getNode()->getOperand(0), AM) &&
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!MatchAddress(N.getNode()->getOperand(1), AM))
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return false;
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AM = Backup;
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if (!MatchAddress(N.getNode()->getOperand(1), AM) &&
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!MatchAddress(N.getNode()->getOperand(0), AM))
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return false;
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AM = Backup;
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break;
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}
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case ISD::OR:
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// Handle "X | C" as "X + C" iff X is known to have C bits clear.
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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MSP430ISelAddressMode Backup = AM;
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uint64_t Offset = CN->getSExtValue();
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// Start with the LHS as an addr mode.
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if (!MatchAddress(N.getOperand(0), AM) &&
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// Address could not have picked a GV address for the displacement.
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AM.GV == NULL &&
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// Check to see if the LHS & C is zero.
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CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
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AM.Disp += Offset;
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return false;
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}
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AM = Backup;
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}
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break;
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}
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return MatchAddressBase(N, AM);
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}
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/// SelectAddr - returns true if it is able pattern match an addressing mode.
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/// It returns the operands which make up the maximal addressing mode it can
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/// match by reference.
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bool MSP430DAGToDAGISel::SelectAddr(SDValue Op, SDValue N,
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SDValue &Base, SDValue &Disp) {
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MSP430ISelAddressMode AM;
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if (MatchAddress(N, AM))
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return false;
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EVT VT = N.getValueType();
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if (AM.BaseType == MSP430ISelAddressMode::RegBase) {
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if (!AM.Base.Reg.getNode())
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AM.Base.Reg = CurDAG->getRegister(0, VT);
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}
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Base = (AM.BaseType == MSP430ISelAddressMode::FrameIndexBase) ?
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CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
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AM.Base.Reg;
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if (AM.GV)
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Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i16, AM.Disp,
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0/*AM.SymbolFlags*/);
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else if (AM.CP)
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Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16,
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AM.Align, AM.Disp, 0/*AM.SymbolFlags*/);
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else if (AM.ES)
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Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/);
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else if (AM.JT != -1)
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Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/);
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else if (AM.BlockAddr)
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Disp = CurDAG->getBlockAddress(AM.BlockAddr, DebugLoc()/*MVT::i32*/,
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true /*AM.SymbolFlags*/);
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else
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Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i16);
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return true;
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}
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@ -3,7 +3,7 @@
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target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
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target triple = "msp430-unknown-unknown"
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@"\010x0021" = common global i8 0, align 1 ; <i8*> [#uses=2]
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@"\010x0021" = external global i8, align 1 ; <i8*> [#uses=2]
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define zeroext i8 @foo(i8 zeroext %x) nounwind {
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entry:
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74
test/CodeGen/MSP430/AddrMode-bis-rx.ll
Normal file
74
test/CodeGen/MSP430/AddrMode-bis-rx.ll
Normal file
@ -0,0 +1,74 @@
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; RUN: llvm-as < %s | llc -march=msp430 | FileCheck %s
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target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
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target triple = "msp430-generic-generic"
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define i16 @am1(i16 %x, i16* %a) nounwind {
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%1 = load i16* %a
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%2 = or i16 %1,%x
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ret i16 %2
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}
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; CHECK: am1:
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; CHECK: bis.w 0(r14), r15
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@foo = external global i16
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define i16 @am2(i16 %x) nounwind {
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%1 = load i16* @foo
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%2 = or i16 %1,%x
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ret i16 %2
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}
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; CHECK: am2:
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; CHECK: bis.w &foo, r15
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@bar = internal constant [2 x i8] [ i8 32, i8 64 ]
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define i8 @am3(i8 %x, i16 %n) nounwind {
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%1 = getelementptr [2 x i8]* @bar, i16 0, i16 %n
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%2 = load i8* %1
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%3 = or i8 %2,%x
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ret i8 %3
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}
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; CHECK: am3:
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; CHECK: bis.b &bar(r14), r15
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define i16 @am4(i16 %x) nounwind {
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%1 = volatile load i16* inttoptr(i16 32 to i16*)
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%2 = or i16 %1,%x
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ret i16 %2
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}
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; CHECK: am4:
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; CHECK: bis.w &32, r15
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define i16 @am5(i16 %x, i16* %a) nounwind {
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%1 = getelementptr i16* %a, i16 2
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%2 = load i16* %1
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%3 = or i16 %2,%x
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ret i16 %3
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}
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; CHECK: am5:
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; CHECK: bis.w 4(r14), r15
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%S = type { i16, i16 }
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@baz = common global %S zeroinitializer, align 1
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define i16 @am6(i16 %x) nounwind {
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%1 = load i16* getelementptr (%S* @baz, i32 0, i32 1)
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%2 = or i16 %1,%x
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ret i16 %2
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}
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; CHECK: am6:
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; CHECK: bis.w &baz+2, r15
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%T = type { i16, [2 x i8] }
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@duh = internal constant %T { i16 16, [2 x i8][i8 32, i8 64 ] }
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define i8 @am7(i8 %x, i16 %n) nounwind {
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%1 = getelementptr %T* @duh, i32 0, i32 1
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%2 = getelementptr [2 x i8]* %1, i16 0, i16 %n
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%3= load i8* %2
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%4 = or i8 %3,%x
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ret i8 %4
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}
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; CHECK: am7:
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; CHECK: bis.b &duh+2(r14), r15
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81
test/CodeGen/MSP430/AddrMode-bis-xr.ll
Normal file
81
test/CodeGen/MSP430/AddrMode-bis-xr.ll
Normal file
@ -0,0 +1,81 @@
|
||||
; RUN: llvm-as < %s | llc -march=msp430 | FileCheck %s
|
||||
target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:16"
|
||||
target triple = "msp430-generic-generic"
|
||||
|
||||
define void @am1(i16* %a, i16 %x) nounwind {
|
||||
%1 = load i16* %a
|
||||
%2 = or i16 %x, %1
|
||||
store i16 %2, i16* %a
|
||||
ret void
|
||||
}
|
||||
; CHECK: am1:
|
||||
; CHECK: bis.w r14, 0(r15)
|
||||
|
||||
@foo = external global i16
|
||||
|
||||
define void @am2(i16 %x) nounwind {
|
||||
%1 = load i16* @foo
|
||||
%2 = or i16 %x, %1
|
||||
store i16 %2, i16* @foo
|
||||
ret void
|
||||
}
|
||||
; CHECK: am2:
|
||||
; CHECK: bis.w r15, &foo
|
||||
|
||||
@bar = external global [2 x i8]
|
||||
|
||||
define void @am3(i16 %i, i8 %x) nounwind {
|
||||
%1 = getelementptr [2 x i8]* @bar, i16 0, i16 %i
|
||||
%2 = load i8* %1
|
||||
%3 = or i8 %x, %2
|
||||
store i8 %3, i8* %1
|
||||
ret void
|
||||
}
|
||||
; CHECK: am3:
|
||||
; CHECK: bis.b r14, &bar(r15)
|
||||
|
||||
define void @am4(i16 %x) nounwind {
|
||||
%1 = volatile load i16* inttoptr(i16 32 to i16*)
|
||||
%2 = or i16 %x, %1
|
||||
volatile store i16 %2, i16* inttoptr(i16 32 to i16*)
|
||||
ret void
|
||||
}
|
||||
; CHECK: am4:
|
||||
; CHECK: bis.w r15, &32
|
||||
|
||||
define void @am5(i16* %a, i16 %x) readonly {
|
||||
%1 = getelementptr inbounds i16* %a, i16 2
|
||||
%2 = load i16* %1
|
||||
%3 = or i16 %x, %2
|
||||
store i16 %3, i16* %1
|
||||
ret void
|
||||
}
|
||||
; CHECK: am5:
|
||||
; CHECK: bis.w r14, 4(r15)
|
||||
|
||||
%S = type { i16, i16 }
|
||||
@baz = common global %S zeroinitializer
|
||||
|
||||
define void @am6(i16 %x) nounwind {
|
||||
%1 = load i16* getelementptr (%S* @baz, i32 0, i32 1)
|
||||
%2 = or i16 %x, %1
|
||||
store i16 %2, i16* getelementptr (%S* @baz, i32 0, i32 1)
|
||||
ret void
|
||||
}
|
||||
; CHECK: am6:
|
||||
; CHECK: bis.w r15, &baz+2
|
||||
|
||||
%T = type { i16, [2 x i8] }
|
||||
@duh = external global %T
|
||||
|
||||
define void @am7(i16 %n, i8 %x) nounwind {
|
||||
%1 = getelementptr %T* @duh, i32 0, i32 1
|
||||
%2 = getelementptr [2 x i8]* %1, i16 0, i16 %n
|
||||
%3 = load i8* %2
|
||||
%4 = or i8 %x, %3
|
||||
store i8 %4, i8* %2
|
||||
ret void
|
||||
}
|
||||
; CHECK: am7:
|
||||
; CHECK: bis.b r14, &duh+2(r15)
|
||||
|
||||
67
test/CodeGen/MSP430/AddrMode-mov-rx.ll
Normal file
67
test/CodeGen/MSP430/AddrMode-mov-rx.ll
Normal file
@ -0,0 +1,67 @@
|
||||
; RUN: llvm-as < %s | llc -march=msp430 | FileCheck %s
|
||||
target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
|
||||
target triple = "msp430-generic-generic"
|
||||
|
||||
define i16 @am1(i16* %a) nounwind {
|
||||
%1 = load i16* %a
|
||||
ret i16 %1
|
||||
}
|
||||
; CHECK: am1:
|
||||
; CHECK: mov.w 0(r15), r15
|
||||
|
||||
@foo = external global i16
|
||||
|
||||
define i16 @am2() nounwind {
|
||||
%1 = load i16* @foo
|
||||
ret i16 %1
|
||||
}
|
||||
; CHECK: am2:
|
||||
; CHECK: mov.w &foo, r15
|
||||
|
||||
@bar = internal constant [2 x i8] [ i8 32, i8 64 ]
|
||||
|
||||
define i8 @am3(i16 %n) nounwind {
|
||||
%1 = getelementptr [2 x i8]* @bar, i16 0, i16 %n
|
||||
%2 = load i8* %1
|
||||
ret i8 %2
|
||||
}
|
||||
; CHECK: am3:
|
||||
; CHECK: mov.b &bar(r15), r15
|
||||
|
||||
define i16 @am4() nounwind {
|
||||
%1 = volatile load i16* inttoptr(i16 32 to i16*)
|
||||
ret i16 %1
|
||||
}
|
||||
; CHECK: am4:
|
||||
; CHECK: mov.w &32, r15
|
||||
|
||||
define i16 @am5(i16* %a) nounwind {
|
||||
%1 = getelementptr i16* %a, i16 2
|
||||
%2 = load i16* %1
|
||||
ret i16 %2
|
||||
}
|
||||
; CHECK: am5:
|
||||
; CHECK: mov.w 4(r15), r15
|
||||
|
||||
%S = type { i16, i16 }
|
||||
@baz = common global %S zeroinitializer, align 1
|
||||
|
||||
define i16 @am6() nounwind {
|
||||
%1 = load i16* getelementptr (%S* @baz, i32 0, i32 1)
|
||||
ret i16 %1
|
||||
}
|
||||
; CHECK: am6:
|
||||
; CHECK: mov.w &baz+2, r15
|
||||
|
||||
%T = type { i16, [2 x i8] }
|
||||
@duh = internal constant %T { i16 16, [2 x i8][i8 32, i8 64 ] }
|
||||
|
||||
define i8 @am7(i16 %n) nounwind {
|
||||
%1 = getelementptr %T* @duh, i32 0, i32 1
|
||||
%2 = getelementptr [2 x i8]* %1, i16 0, i16 %n
|
||||
%3= load i8* %2
|
||||
ret i8 %3
|
||||
}
|
||||
; CHECK: am7:
|
||||
; CHECK: mov.b &duh+2(r15), r15
|
||||
|
||||
67
test/CodeGen/MSP430/AddrMode-mov-xr.ll
Normal file
67
test/CodeGen/MSP430/AddrMode-mov-xr.ll
Normal file
@ -0,0 +1,67 @@
|
||||
; RUN: llvm-as < %s | llc -march=msp430 | FileCheck %s
|
||||
target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
|
||||
target triple = "msp430-generic-generic"
|
||||
|
||||
define void @am1(i16* %a, i16 %b) nounwind {
|
||||
store i16 %b, i16* %a
|
||||
ret void
|
||||
}
|
||||
; CHECK: am1:
|
||||
; CHECK: mov.w r14, 0(r15)
|
||||
|
||||
@foo = external global i16
|
||||
|
||||
define void @am2(i16 %a) nounwind {
|
||||
store i16 %a, i16* @foo
|
||||
ret void
|
||||
}
|
||||
; CHECK: am2:
|
||||
; CHECK: mov.w r15, &foo
|
||||
|
||||
@bar = external global [2 x i8]
|
||||
|
||||
define void @am3(i16 %i, i8 %a) nounwind {
|
||||
%1 = getelementptr [2 x i8]* @bar, i16 0, i16 %i
|
||||
store i8 %a, i8* %1
|
||||
ret void
|
||||
}
|
||||
; CHECK: am3:
|
||||
; CHECK: mov.b r14, &bar(r15)
|
||||
|
||||
define void @am4(i16 %a) nounwind {
|
||||
volatile store i16 %a, i16* inttoptr(i16 32 to i16*)
|
||||
ret void
|
||||
}
|
||||
; CHECK: am4:
|
||||
; CHECK: mov.w r15, &32
|
||||
|
||||
define void @am5(i16* nocapture %p, i16 %a) nounwind readonly {
|
||||
%1 = getelementptr inbounds i16* %p, i16 2
|
||||
store i16 %a, i16* %1
|
||||
ret void
|
||||
}
|
||||
; CHECK: am5:
|
||||
; CHECK: mov.w r14, 4(r15)
|
||||
|
||||
%S = type { i16, i16 }
|
||||
@baz = common global %S zeroinitializer, align 1
|
||||
|
||||
define void @am6(i16 %a) nounwind {
|
||||
store i16 %a, i16* getelementptr (%S* @baz, i32 0, i32 1)
|
||||
ret void
|
||||
}
|
||||
; CHECK: am6:
|
||||
; CHECK: mov.w r15, &baz+2
|
||||
|
||||
%T = type { i16, [2 x i8] }
|
||||
@duh = external global %T
|
||||
|
||||
define void @am7(i16 %n, i8 %a) nounwind {
|
||||
%1 = getelementptr %T* @duh, i32 0, i32 1
|
||||
%2 = getelementptr [2 x i8]* %1, i16 0, i16 %n
|
||||
store i8 %a, i8* %2
|
||||
ret void
|
||||
}
|
||||
; CHECK: am7:
|
||||
; CHECK: mov.b r14, &duh+2(r15)
|
||||
|
||||
@ -20,6 +20,7 @@ define void @immmem() nounwind {
|
||||
}
|
||||
|
||||
define void @mem() nounwind {
|
||||
call void asm sideeffect "bic\09$0,r2", "m"(i16* @foo) nounwind
|
||||
%fooval = load i16* @foo
|
||||
call void asm sideeffect "bic\09$0,r2", "m"(i16 %fooval) nounwind
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user