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https://github.com/c64scene-ar/llvm-6502.git
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fix some 80-col violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55571 91177308-0d34-0410-b5e6-96231b3b80d8
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07cabf6102
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@ -1196,7 +1196,8 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
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N0.getNode()->hasOneUse()) {
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N0.getNode()->hasOneUse()) {
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Sh = N0; Y = N1;
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Sh = N0; Y = N1;
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} else if (N1.getOpcode() == ISD::SHL &&
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} else if (N1.getOpcode() == ISD::SHL &&
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isa<ConstantSDNode>(N1.getOperand(1)) && N1.getNode()->hasOneUse()) {
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isa<ConstantSDNode>(N1.getOperand(1)) &&
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N1.getNode()->hasOneUse()) {
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Sh = N1; Y = N0;
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Sh = N1; Y = N0;
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}
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}
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if (Sh.getNode()) {
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if (Sh.getNode()) {
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@ -2068,10 +2069,8 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) {
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// (rotl x, (sub 32, y))
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// (rotl x, (sub 32, y))
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if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
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if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
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if (SUBC->getAPIntValue() == OpSizeInBits) {
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if (SUBC->getAPIntValue() == OpSizeInBits) {
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if (HasROTL)
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return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, VT, LHSShiftArg,
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return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode();
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HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
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else
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return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode();
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}
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}
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}
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}
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} else if (LExtOp0.getOpcode() == ISD::SUB &&
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} else if (LExtOp0.getOpcode() == ISD::SUB &&
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@ -2082,10 +2081,8 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) {
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// (rotr x, (sub 32, y))
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// (rotr x, (sub 32, y))
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if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
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if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
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if (SUBC->getAPIntValue() == OpSizeInBits) {
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if (SUBC->getAPIntValue() == OpSizeInBits) {
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if (HasROTL)
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return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
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return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).getNode();
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HasROTL ? RHSShiftAmt : LHSShiftAmt).getNode();
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else
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return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode();
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}
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}
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}
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}
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}
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}
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@ -2144,7 +2141,8 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
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}
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}
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// fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
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// fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
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if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
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if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
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N0.getNode()->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
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N0.getNode()->hasOneUse() &&
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isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
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SDValue V = N0.getOperand(0);
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SDValue V = N0.getOperand(0);
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V = DAG.getNode(ISD::XOR, V.getValueType(), V,
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V = DAG.getNode(ISD::XOR, V.getValueType(), V,
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DAG.getConstant(1, V.getValueType()));
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DAG.getConstant(1, V.getValueType()));
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@ -2426,7 +2424,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
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// If the shift is not a no-op (in which case this should be just a sign
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// If the shift is not a no-op (in which case this should be just a sign
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// extend already), the truncated to type is legal, sign_extend is legal
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// extend already), the truncated to type is legal, sign_extend is legal
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// on that type, and the the truncate to that type is both legal and free,
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// on that type, and the the truncate to that type is both legal and free,
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// perform the transform.
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// perform the transform.
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if (ShiftAmt &&
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if (ShiftAmt &&
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TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) &&
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TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) &&
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@ -2746,7 +2744,8 @@ static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
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TargetLowering &TLI) {
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TargetLowering &TLI) {
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bool HasCopyToRegUses = false;
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bool HasCopyToRegUses = false;
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bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
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bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
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for (SDNode::use_iterator UI = N0.getNode()->use_begin(), UE = N0.getNode()->use_end();
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for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
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UE = N0.getNode()->use_end();
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UI != UE; ++UI) {
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UI != UE; ++UI) {
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SDNode *User = *UI;
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SDNode *User = *UI;
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if (User == N)
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if (User == N)
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@ -2916,7 +2915,8 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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LN0->isVolatile(),
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LN0->isVolatile(),
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LN0->getAlignment());
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LN0->getAlignment());
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CombineTo(N, ExtLoad);
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CombineTo(N, ExtLoad);
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CombineTo(N0.getNode(), DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
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CombineTo(N0.getNode(),
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DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
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ExtLoad.getValue(1));
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ExtLoad.getValue(1));
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return SDValue(N, 0); // Return N so it doesn't get rechecked!
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return SDValue(N, 0); // Return N so it doesn't get rechecked!
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}
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}
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@ -3041,7 +3041,8 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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LN0->isVolatile(),
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LN0->isVolatile(),
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LN0->getAlignment());
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LN0->getAlignment());
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CombineTo(N, ExtLoad);
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CombineTo(N, ExtLoad);
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CombineTo(N0.getNode(), DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
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CombineTo(N0.getNode(),
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DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
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ExtLoad.getValue(1));
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ExtLoad.getValue(1));
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return SDValue(N, 0); // Return N so it doesn't get rechecked!
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return SDValue(N, 0); // Return N so it doesn't get rechecked!
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}
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}
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@ -3514,7 +3515,8 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
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LN0->getSrcValue(), LN0->getSrcValueOffset(),
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LN0->getSrcValue(), LN0->getSrcValueOffset(),
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LN0->isVolatile(), OrigAlign);
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LN0->isVolatile(), OrigAlign);
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AddToWorkList(N);
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AddToWorkList(N);
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CombineTo(N0.getNode(), DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
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CombineTo(N0.getNode(),
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DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
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Load.getValue(1));
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Load.getValue(1));
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return Load;
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return Load;
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}
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}
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@ -4037,7 +4039,8 @@ SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
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// Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
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// Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
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// value of X.
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// value of X.
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if (N0.getOpcode() == ISD::FP_ROUND && N0.getNode()->getConstantOperandVal(1) == 1){
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if (N0.getOpcode() == ISD::FP_ROUND
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&& N0.getNode()->getConstantOperandVal(1) == 1) {
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SDValue In = N0.getOperand(0);
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SDValue In = N0.getOperand(0);
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if (In.getValueType() == VT) return In;
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if (In.getValueType() == VT) return In;
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if (VT.bitsLT(In.getValueType()))
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if (VT.bitsLT(In.getValueType()))
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@ -4057,8 +4060,8 @@ SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
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LN0->isVolatile(),
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LN0->isVolatile(),
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LN0->getAlignment());
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LN0->getAlignment());
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CombineTo(N, ExtLoad);
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CombineTo(N, ExtLoad);
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CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad,
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CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(),
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DAG.getIntPtrConstant(1)),
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ExtLoad, DAG.getIntPtrConstant(1)),
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ExtLoad.getValue(1));
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ExtLoad.getValue(1));
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return SDValue(N, 0); // Return N so it doesn't get rechecked!
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return SDValue(N, 0); // Return N so it doesn't get rechecked!
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}
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}
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@ -4772,7 +4775,8 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
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// vector with the inserted element.
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// vector with the inserted element.
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if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
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if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
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unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
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unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
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SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), InVec.getNode()->op_end());
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SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
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InVec.getNode()->op_end());
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if (Elt < Ops.size())
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if (Elt < Ops.size())
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Ops[Elt] = InVal;
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Ops[Elt] = InVal;
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return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
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return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
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