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https://github.com/c64scene-ar/llvm-6502.git
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[AArch64] Use [SU]ABSDIFF nodes instead of intrinsics for ABD/ABA
No functional change, but it preps codegen for the future when SABSDIFF will start getting generated in anger. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242545 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
James Molloy
parent
8a8582d6e9
commit
126ab2389e
@ -683,10 +683,12 @@ void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
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setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
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setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
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// [SU][MIN|MAX] are available for all NEON types apart from i64.
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// [SU][MIN|MAX] and [SU]ABSDIFF are available for all NEON types apart from
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// i64.
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if (!VT.isFloatingPoint() &&
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VT.getSimpleVT() != MVT::v2i64 && VT.getSimpleVT() != MVT::v1i64)
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for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
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for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX,
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ISD::SABSDIFF, ISD::UABSDIFF})
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setOperationAction(Opcode, VT.getSimpleVT(), Legal);
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if (Subtarget->isLittleEndian()) {
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@ -8063,14 +8065,15 @@ static SDValue performAddSubLongCombine(SDNode *N,
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// (aarch64_neon_umull (extract_high (v2i64 vec)))
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// (extract_high (v2i64 (dup128 scalar)))))
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//
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static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
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static SDValue tryCombineLongOpWithDup(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI,
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SelectionDAG &DAG) {
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if (DCI.isBeforeLegalizeOps())
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return SDValue();
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SDValue LHS = N->getOperand(1);
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SDValue RHS = N->getOperand(2);
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bool IsIntrinsic = N->getOpcode() == ISD::INTRINSIC_WO_CHAIN;
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SDValue LHS = N->getOperand(IsIntrinsic ? 1 : 0);
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SDValue RHS = N->getOperand(IsIntrinsic ? 2 : 1);
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assert(LHS.getValueType().is64BitVector() &&
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RHS.getValueType().is64BitVector() &&
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"unexpected shape for long operation");
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@ -8088,8 +8091,13 @@ static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
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return SDValue();
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}
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
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N->getOperand(0), LHS, RHS);
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// N could either be an intrinsic or a sabsdiff/uabsdiff node.
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if (IsIntrinsic)
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
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N->getOperand(0), LHS, RHS);
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else
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return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
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LHS, RHS);
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}
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static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
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@ -8208,11 +8216,17 @@ static SDValue performIntrinsicCombine(SDNode *N,
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case Intrinsic::aarch64_neon_fmin:
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return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
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N->getOperand(1), N->getOperand(2));
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case Intrinsic::aarch64_neon_sabd:
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return DAG.getNode(ISD::SABSDIFF, SDLoc(N), N->getValueType(0),
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N->getOperand(1), N->getOperand(2));
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case Intrinsic::aarch64_neon_uabd:
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return DAG.getNode(ISD::UABSDIFF, SDLoc(N), N->getValueType(0),
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N->getOperand(1), N->getOperand(2));
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case Intrinsic::aarch64_neon_smull:
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case Intrinsic::aarch64_neon_umull:
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case Intrinsic::aarch64_neon_pmull:
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case Intrinsic::aarch64_neon_sqdmull:
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return tryCombineLongOpWithDup(IID, N, DCI, DAG);
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return tryCombineLongOpWithDup(N, DCI, DAG);
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case Intrinsic::aarch64_neon_sqshl:
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case Intrinsic::aarch64_neon_uqshl:
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case Intrinsic::aarch64_neon_sqshlu:
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@ -8237,18 +8251,15 @@ static SDValue performExtendCombine(SDNode *N,
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// helps the backend to decide that an sabdl2 would be useful, saving a real
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// extract_high operation.
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if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
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N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
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(N->getOperand(0).getOpcode() == ISD::SABSDIFF ||
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N->getOperand(0).getOpcode() == ISD::UABSDIFF)) {
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SDNode *ABDNode = N->getOperand(0).getNode();
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unsigned IID = getIntrinsicID(ABDNode);
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if (IID == Intrinsic::aarch64_neon_sabd ||
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IID == Intrinsic::aarch64_neon_uabd) {
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SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
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if (!NewABD.getNode())
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return SDValue();
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SDValue NewABD = tryCombineLongOpWithDup(ABDNode, DCI, DAG);
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if (!NewABD.getNode())
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return SDValue();
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return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
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NewABD);
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}
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return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
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NewABD);
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}
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// This is effectively a custom type legalization for AArch64.
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@ -2843,8 +2843,8 @@ defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
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defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
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defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
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defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
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TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >;
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defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>;
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TriOpFrag<(add node:$LHS, (sabsdiff node:$MHS, node:$RHS))> >;
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defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", sabsdiff>;
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defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
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defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
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defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
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@ -2862,8 +2862,8 @@ defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
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defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
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defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
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defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
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TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >;
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defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>;
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TriOpFrag<(add node:$LHS, (uabsdiff node:$MHS, node:$RHS))> >;
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defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", uabsdiff>;
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defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
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defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
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defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
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@ -3381,9 +3381,9 @@ defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn
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defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
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defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
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defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
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int_aarch64_neon_sabd>;
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sabsdiff>;
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defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
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int_aarch64_neon_sabd>;
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sabsdiff>;
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defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
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BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
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defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
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@ -3404,9 +3404,9 @@ defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
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defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
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BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
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defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
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int_aarch64_neon_uabd>;
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uabsdiff>;
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defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
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int_aarch64_neon_uabd>;
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uabsdiff>;
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defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
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BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
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defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
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