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ARM64: add constraints to various FastISel operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206284 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -225,7 +225,7 @@ unsigned ARM64FastISel::ARM64MaterializeFP(const ConstantFP *CFP, MVT VT) {
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Align = DL.getTypeAllocSize(CFP->getType());
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unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
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unsigned ADRPReg = createResultReg(&ARM64::GPR64RegClass);
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unsigned ADRPReg = createResultReg(&ARM64::GPR64commonRegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ADRP),
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ADRPReg).addConstantPoolIndex(Idx, 0, ARM64II::MO_PAGE);
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@ -253,25 +253,28 @@ unsigned ARM64FastISel::ARM64MaterializeGV(const GlobalValue *GV) {
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EVT DestEVT = TLI.getValueType(GV->getType(), true);
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if (!DestEVT.isSimple())
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return 0;
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MVT DestVT = DestEVT.getSimpleVT();
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unsigned ADRPReg = createResultReg(&ARM64::GPR64RegClass);
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unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
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unsigned ADRPReg = createResultReg(&ARM64::GPR64commonRegClass);
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unsigned ResultReg;
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if (OpFlags & ARM64II::MO_GOT) {
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// ADRP + LDRX
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ADRP),
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ADRPReg)
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.addGlobalAddress(GV, 0, ARM64II::MO_GOT | ARM64II::MO_PAGE);
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ResultReg = createResultReg(&ARM64::GPR64RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::LDRXui),
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ResultReg)
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.addReg(ADRPReg)
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.addGlobalAddress(GV, 0, ARM64II::MO_GOT | ARM64II::MO_PAGEOFF |
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ARM64II::MO_NC);
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ARM64II::MO_NC);
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} else {
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// ADRP + ADDX
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ADRP),
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ADRPReg).addGlobalAddress(GV, 0, ARM64II::MO_PAGE);
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ResultReg = createResultReg(&ARM64::GPR64spRegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ADDXri),
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ResultReg)
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.addReg(ADRPReg)
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@ -1117,7 +1120,8 @@ bool ARM64FastISel::SelectFPToInt(const Instruction *I, bool Signed) {
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else
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Opc = (DestVT == MVT::i32) ? ARM64::FCVTZUUWSr : ARM64::FCVTZUUXSr;
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}
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unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
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unsigned ResultReg = createResultReg(
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DestVT == MVT::i32 ? &ARM64::GPR32RegClass : &ARM64::GPR64RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
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.addReg(SrcReg);
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UpdateValueMap(I, ResultReg);
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@ -1143,6 +1147,9 @@ bool ARM64FastISel::SelectIntToFP(const Instruction *I, bool Signed) {
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return false;
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}
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MRI.constrainRegClass(SrcReg, SrcVT == MVT::i64 ? &ARM64::GPR64RegClass
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: &ARM64::GPR32RegClass);
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unsigned Opc;
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if (SrcVT == MVT::i64) {
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if (Signed)
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@ -1,4 +1,8 @@
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; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -O0 | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-apple-ios7.0 -O0
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; (The O0 test is to make sure FastISel still constrains its operands properly
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; and the verifier doesn't trigger).
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@var32 = global i32 0
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@var64 = global i64 0
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@ -7,8 +7,9 @@
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@.str3 = private unnamed_addr constant [7 x i8] c"%f %u\0A\00", align 1
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define void @testDouble(double %d) ssp {
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; CHECK: fcvtzu x{{.}}, d{{.}}
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; CHECK: fcvtzu w{{.}}, d{{.}}
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; CHECK-LABEL: testDouble:
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; CHECK: fcvtzu x{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: fcvtzu w{{[0-9]+}}, d{{[0-9]+}}
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entry:
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%d.addr = alloca double, align 8
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store double %d, double* %d.addr, align 8
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@ -26,8 +27,9 @@ entry:
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declare i32 @printf(i8*, ...)
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define void @testFloat(float %f) ssp {
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; CHECK: fcvtzu x{{.}}, s{{.}}
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; CHECK: fcvtzu w{{.}}, s{{.}}
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; CHECK-LABEL: testFloat:
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; CHECK: fcvtzu x{{[0-9]+}}, s{{[0-9]+}}
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; CHECK: fcvtzu w{{[0-9]+}}, s{{[0-9]+}}
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entry:
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%f.addr = alloca float, align 4
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store float %f, float* %f.addr, align 4
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