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Allow target to specify register output dependency. Still default to one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146547 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -648,6 +648,16 @@ public:
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SDNode *DefNode, unsigned DefIdx,
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SDNode *UseNode, unsigned UseIdx) const;
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/// getOutputLatency - Compute and return the output dependency latency of a
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/// a given pair of defs which both target the same register. This is usually
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/// one.
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virtual unsigned getOutputLatency(const InstrItineraryData *ItinData,
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const MachineInstr *DefMI1,
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const MachineInstr *DefMI2,
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unsigned Reg) const {
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return 1;
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}
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/// getInstrLatency - Compute the instruction latency of a given instruction.
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/// If the instruction has higher cost when predicated, it's returned via
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/// PredCost.
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@ -278,7 +278,13 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
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if (DefSU != SU &&
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(Kind != SDep::Output || !MO.isDead() ||
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!DefSU->getInstr()->registerDefIsDead(Reg))) {
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DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/Reg));
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if (Kind == SDep::Anti)
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DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/Reg));
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else {
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unsigned AOLat = TII->getOutputLatency(InstrItins, MI,
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DefSU->getInstr(), Reg);
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DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/Reg));
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}
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}
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}
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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