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Maintain consistency in negating things
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22855 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -352,19 +352,18 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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// 'not', then fold 'or' into 'nor', and so forth for the supported ops.
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if (isOprNot(N)) {
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unsigned Opc;
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switch(N->getOperand(0).getOpcode()) {
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SDOperand Val = Select(N->getOperand(0));
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switch (Val.getTargetOpcode()) {
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default: Opc = 0; break;
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case ISD::OR: Opc = PPC::NOR; break;
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case ISD::AND: Opc = PPC::NAND; break;
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case ISD::XOR: Opc = PPC::EQV; break;
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case PPC::OR: Opc = PPC::NOR; break;
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case PPC::AND: Opc = PPC::NAND; break;
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case PPC::XOR: Opc = PPC::EQV; break;
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}
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if (Opc)
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CurDAG->SelectNodeTo(N, MVT::i32, Opc,
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Select(N->getOperand(0).getOperand(0)),
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Select(N->getOperand(0).getOperand(1)));
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CurDAG->SelectNodeTo(N, MVT::i32, Opc, Val.getOperand(0),
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Val.getOperand(1));
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else
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::NOR, Select(N->getOperand(0)),
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Select(N->getOperand(0)));
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::NOR, Val, Val);
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break;
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}
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// If this is a xor with an immediate other than -1, then codegen it as high
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