From 132183510f3db502c7d837ee0dc40221b5c6245e Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Mon, 3 Jun 2013 17:39:43 +0000 Subject: [PATCH] R600/SI: Add support for global loads git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183131 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/AMDGPUInstructions.td | 4 ++ lib/Target/R600/SIInstrInfo.td | 9 +++-- lib/Target/R600/SIInstructions.td | 30 ++++++++++++++- test/CodeGen/R600/load.ll | 54 +++++++++++++++++++++++++-- 4 files changed, 89 insertions(+), 8 deletions(-) diff --git a/lib/Target/R600/AMDGPUInstructions.td b/lib/Target/R600/AMDGPUInstructions.td index 54df7d0b1fd..29df37499a2 100644 --- a/lib/Target/R600/AMDGPUInstructions.td +++ b/lib/Target/R600/AMDGPUInstructions.td @@ -90,6 +90,10 @@ def zextloadi8_global : PatFrag<(ops node:$ptr), (zextloadi8 node:$ptr), [{ return isGlobalLoad(dyn_cast(N)); }]>; +def zextloadi8_constant : PatFrag<(ops node:$ptr), (zextloadi8 node:$ptr), [{ + return isGlobalLoad(dyn_cast(N)); +}]>; + class Constants { int TWO_PI = 0x40c90fdb; int PI = 0x40490fdb; diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index 19d9de1ffc8..cb159baef13 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -35,9 +35,12 @@ def IMM8bitDWORD : ImmLeaf < }]> >; -def IMM12bit : ImmLeaf < - i16, - [{return isUInt<12>(Imm);}] +def as_i16imm : SDNodeXFormgetTargetConstant(N->getSExtValue(), MVT::i16); +}]>; + +def IMM12bit : PatLeaf <(imm), + [{return isUInt<12>(N->getZExtValue());}] >; class InlineImm : PatLeaf <(vt imm), [{ diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index c739e2ad572..b6db815d365 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -399,7 +399,7 @@ defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMA //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>; //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>; //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>; -//def BUFFER_LOAD_UBYTE : MUBUF_ <0x00000008, "BUFFER_LOAD_UBYTE", []>; +defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>; //def BUFFER_LOAD_SBYTE : MUBUF_ <0x00000009, "BUFFER_LOAD_SBYTE", []>; //def BUFFER_LOAD_USHORT : MUBUF_ <0x0000000a, "BUFFER_LOAD_USHORT", []>; //def BUFFER_LOAD_SSHORT : MUBUF_ <0x0000000b, "BUFFER_LOAD_SSHORT", []>; @@ -1611,6 +1611,34 @@ defm : SMRD_Pattern ; // MUBUF Patterns //===----------------------------------------------------------------------===// +multiclass MUBUFLoad_Pattern { + def : Pat < + (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))), + (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset)) + >; + + def : Pat < + (vt (global_ld i64:$ptr)), + (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0) + >; + + def : Pat < + (vt (global_ld (add i64:$ptr, i64:$offset))), + (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) + >; + + def : Pat < + (vt (constant_ld (add i64:$ptr, i64:$offset))), + (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) + >; +} + +defm : MUBUFLoad_Pattern ; +defm : MUBUFLoad_Pattern ; + multiclass MUBUFStore_Pattern { def : Pat < diff --git a/test/CodeGen/R600/load.ll b/test/CodeGen/R600/load.ll index b03245ae87b..ff774ec922d 100644 --- a/test/CodeGen/R600/load.ll +++ b/test/CodeGen/R600/load.ll @@ -1,8 +1,12 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s ; Load an i8 value from the global address space. -; CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} +; R600-CHECK: @load_i8 +; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} +; SI-CHECK: @load_i8 +; SI-CHECK: BUFFER_LOAD_UBYTE VGPR{{[0-9]+}}, define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { %1 = load i8 addrspace(1)* %in %2 = zext i8 %1 to i32 @@ -10,9 +14,51 @@ define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { ret void } -; Load a f32 value from the constant address space. -; CHECK: VTX_READ_32 T{{[0-9]+\.X, T[0-9]+\.X}} +; load an i32 value from the global address space. +; R600-CHECK: @load_i32 +; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 +; SI-CHECK: @load_i32 +; SI-CHECK: BUFFER_LOAD_DWORD VGPR{{[0-9]+}} +define void @load_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { +entry: + %0 = load i32 addrspace(1)* %in + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; load a f32 value from the global address space. +; R600-CHECK: @load_f32 +; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 + +; SI-CHECK: @load_f32 +; SI-CHECK: BUFFER_LOAD_DWORD VGPR{{[0-9]+}} +define void @load_f32(float addrspace(1)* %out, float addrspace(1)* %in) { +entry: + %0 = load float addrspace(1)* %in + store float %0, float addrspace(1)* %out + ret void +} + +; Load an i32 value from the constant address space. +; R600-CHECK: @load_const_addrspace_i32 +; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 + +; SI-CHECK: @load_const_addrspace_i32 +; SI-CHECK: S_LOAD_DWORD SGPR{{[0-9]+}} +define void @load_const_addrspace_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { +entry: + %0 = load i32 addrspace(2)* %in + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; Load a f32 value from the constant address space. +; R600-CHECK: @load_const_addrspace_f32 +; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 + +; SI-CHECK: @load_const_addrspace_f32 +; SI-CHECK: S_LOAD_DWORD SGPR{{[0-9]+}} define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace(2)* %in) { %1 = load float addrspace(2)* %in store float %1, float addrspace(1)* %out