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Teach DAG combine to fold (extract_subvec (concat v1, ..) i) to v_i
- If the extracted vector has the same type of all vectored being concatenated together, it should be simplified directly into v_i, where i is the index of the element being extracted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166125 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -8610,8 +8610,8 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
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return SDValue();
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// Only handle cases where both indexes are constants with the same type.
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ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
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ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
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ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
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ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
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if (InsIdx && ExtIdx &&
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InsIdx->getValueType(0).getSizeInBits() <= 64 &&
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@ -8628,6 +8628,21 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
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}
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}
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if (V->getOpcode() == ISD::CONCAT_VECTORS) {
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// Combine:
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// (extract_subvec (concat V1, V2, ...), i)
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// Into:
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// Vi if possible
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for (unsigned i = 0, e = V->getNumOperands(); i != e; ++i)
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if (V->getOperand(i).getValueType() != NVT)
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return SDValue();
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unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
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unsigned NumElems = NVT.getVectorNumElements();
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assert((Idx % NumElems) == 0 &&
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"IDX in concat is not a multiple of the result vector length.");
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return V->getOperand(Idx / NumElems);
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}
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return SDValue();
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}
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17
test/CodeGen/X86/extract-concat.ll
Normal file
17
test/CodeGen/X86/extract-concat.ll
Normal file
@ -0,0 +1,17 @@
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; RUN: llc < %s -mcpu=corei7 -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
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define void @foo(<4 x float> %in, <4 x i8>* %out) {
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%t0 = fptoui <4 x float> %in to <4 x i32>
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%t1 = trunc <4 x i32> %t0 to <4 x i16>
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%t2 = shufflevector <4 x i16> %t1, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%t3 = trunc <8 x i16> %t2 to <8 x i8>
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%t4 = shufflevector <8 x i8> %t3, <8 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%t5 = insertelement <4 x i8> %t4, i8 -1, i32 3
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store <4 x i8> %t5, <4 x i8>* %out
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ret void
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; CHECK: foo
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; CHECK: cvttps2dq
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; CHECK-NOT: pextrd
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; CHECK: pshufb
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; CHECK: ret
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}
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