mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
Clean up the ARM asm parser a bit.
No intendeded functional change. Just cleaning up a bit to make things more self-consistent in layout and style. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136095 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
3d5ab367b6
commit
1355cf1f76
@ -600,7 +600,7 @@ class AI3ldstidxT<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
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let Inst{11-8} = addr{7-4}; // imm7_4/zero
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let Inst{7-4} = op;
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let Inst{3-0} = addr{3-0}; // imm3_0/Rm
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let AsmMatchConverter = "CvtLdWriteBackRegAddrMode3";
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let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
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}
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class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops,
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@ -1853,7 +1853,7 @@ multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
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let Inst{23} = addr{12};
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let Inst{19-16} = addr{17-14};
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let Inst{11-0} = addr{11-0};
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let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
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let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
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}
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def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins GPR:$Rn, am2offset:$offset),
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@ -1950,7 +1950,7 @@ def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
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let Inst{21} = 1; // overwrite
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let Inst{19-16} = addr{17-14};
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let Inst{11-0} = addr{11-0};
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let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
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let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
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}
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def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
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(ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
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@ -1965,7 +1965,7 @@ def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
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let Inst{21} = 1; // overwrite
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let Inst{19-16} = addr{17-14};
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let Inst{11-0} = addr{11-0};
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let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
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let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
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}
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def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
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(ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
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@ -2068,7 +2068,7 @@ def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
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"strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{21} = 1; // overwrite
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let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
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let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
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}
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def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
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@ -2076,7 +2076,7 @@ def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
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"strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{21} = 1; // overwrite
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let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
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let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
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}
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def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
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@ -2084,7 +2084,7 @@ def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
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"strht", "\t$Rt, $addr", "$addr.base = $base_wb",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{21} = 1; // overwrite
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let AsmMatchConverter = "CvtStWriteBackRegAddrMode3";
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let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
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}
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//===----------------------------------------------------------------------===//
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@ -47,20 +47,19 @@ class ARMAsmParser : public MCTargetAsmParser {
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void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
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bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
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int TryParseRegister();
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virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
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bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
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int TryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &,
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int tryParseRegister();
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bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
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int tryparseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &,
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ARMII::AddrMode AddrMode);
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bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
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bool ParsePrefix(ARMMCExpr::VariantKind &RefKind);
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const MCExpr *ApplyPrefixToExpr(const MCExpr *E,
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bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
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bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
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const MCExpr *applyPrefixToExpr(const MCExpr *E,
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MCSymbolRefExpr::VariantKind Variant);
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bool ParseMemoryOffsetReg(bool &Negative,
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bool parseMemoryOffsetReg(bool &Negative,
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bool &OffsetRegShifted,
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enum ARM_AM::ShiftOpc &ShiftType,
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const MCExpr *&ShiftAmount,
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@ -68,20 +67,17 @@ class ARMAsmParser : public MCTargetAsmParser {
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bool &OffsetIsReg,
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int &OffsetRegNum,
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SMLoc &E);
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bool ParseShift(enum ARM_AM::ShiftOpc &St,
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bool parseShift(enum ARM_AM::ShiftOpc &St,
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const MCExpr *&ShiftAmount, SMLoc &E);
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bool ParseDirectiveWord(unsigned Size, SMLoc L);
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bool ParseDirectiveThumb(SMLoc L);
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bool ParseDirectiveThumbFunc(SMLoc L);
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bool ParseDirectiveCode(SMLoc L);
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bool ParseDirectiveSyntax(SMLoc L);
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bool parseDirectiveWord(unsigned Size, SMLoc L);
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bool parseDirectiveThumb(SMLoc L);
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bool parseDirectiveThumbFunc(SMLoc L);
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bool parseDirectiveCode(SMLoc L);
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bool parseDirectiveSyntax(SMLoc L);
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bool MatchAndEmitInstruction(SMLoc IDLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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MCStreamer &Out);
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StringRef SplitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
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StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
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bool &CarrySetting, unsigned &ProcessorIMod);
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void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
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void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
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bool &CanAcceptPredicationCode);
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bool isThumb() const {
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@ -130,13 +126,13 @@ class ARMAsmParser : public MCTargetAsmParser {
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OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
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// Asm Match Converter Methods
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bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
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bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &);
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bool CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
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bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &);
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bool CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
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bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &);
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bool CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
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bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &);
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public:
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@ -148,9 +144,15 @@ public:
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setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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}
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virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
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// Implementation of the MCTargetAsmParser interface:
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bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
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bool ParseInstruction(StringRef Name, SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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virtual bool ParseDirective(AsmToken DirectiveID);
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bool ParseDirective(AsmToken DirectiveID);
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bool MatchAndEmitInstruction(SMLoc IDLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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MCStreamer &Out);
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};
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} // end anonymous namespace
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@ -1207,7 +1209,7 @@ static unsigned MatchRegisterName(StringRef Name);
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bool ARMAsmParser::ParseRegister(unsigned &RegNo,
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SMLoc &StartLoc, SMLoc &EndLoc) {
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RegNo = TryParseRegister();
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RegNo = tryParseRegister();
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return (RegNo == (unsigned)-1);
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}
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@ -1216,7 +1218,7 @@ bool ARMAsmParser::ParseRegister(unsigned &RegNo,
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/// and if it is a register name the token is eaten and the register number is
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/// returned. Otherwise return -1.
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///
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int ARMAsmParser::TryParseRegister() {
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int ARMAsmParser::tryParseRegister() {
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const AsmToken &Tok = Parser.getTok();
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assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
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@ -1244,7 +1246,7 @@ int ARMAsmParser::TryParseRegister() {
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// occurs, return -1. An irrecoverable error is one where tokens have been
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// consumed in the process of trying to parse the shifter (i.e., when it is
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// indeed a shifter operand, but malformed).
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int ARMAsmParser::TryParseShiftRegister(
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int ARMAsmParser::tryparseShiftRegister(
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SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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SMLoc S = Parser.getTok().getLoc();
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const AsmToken &Tok = Parser.getTok();
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@ -1306,7 +1308,7 @@ int ARMAsmParser::TryParseShiftRegister(
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return -1;
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}
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} else if (Parser.getTok().is(AsmToken::Identifier)) {
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ShiftReg = TryParseRegister();
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ShiftReg = tryParseRegister();
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SMLoc L = Parser.getTok().getLoc();
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if (ShiftReg == -1) {
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Error (L, "expected immediate or register in shift operand");
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@ -1338,9 +1340,9 @@ int ARMAsmParser::TryParseShiftRegister(
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/// TODO this is likely to change to allow different register types and or to
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/// parse for a specific register type.
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bool ARMAsmParser::
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TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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SMLoc S = Parser.getTok().getLoc();
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int RegNo = TryParseRegister();
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int RegNo = tryParseRegister();
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if (RegNo == -1)
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return true;
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@ -1438,7 +1440,7 @@ parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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/// Parse a register list, return it if successful else return null. The first
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/// token must be a '{' when called.
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bool ARMAsmParser::
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ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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assert(Parser.getTok().is(AsmToken::LCurly) &&
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"Token is not a Left Curly Brace");
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SMLoc S = Parser.getTok().getLoc();
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@ -1458,7 +1460,7 @@ ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return true;
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}
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int RegNum = TryParseRegister();
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int RegNum = tryParseRegister();
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if (RegNum == -1) {
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Error(RegLoc, "register expected");
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return true;
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@ -1650,7 +1652,7 @@ ARMAsmParser::OperandMatchResultTy ARMAsmParser::
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parseMemMode2Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
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if (ParseMemory(Operands, ARMII::AddrMode2))
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if (parseMemory(Operands, ARMII::AddrMode2))
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return MatchOperand_NoMatch;
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return MatchOperand_Success;
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@ -1661,7 +1663,7 @@ ARMAsmParser::OperandMatchResultTy ARMAsmParser::
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parseMemMode3Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
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if (ParseMemory(Operands, ARMII::AddrMode3))
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if (parseMemory(Operands, ARMII::AddrMode3))
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return MatchOperand_NoMatch;
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return MatchOperand_Success;
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@ -1804,11 +1806,11 @@ parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return MatchOperand_Success;
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}
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/// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
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/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
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/// Needed here because the Asm Gen Matcher can't handle properly tied operands
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/// when they refer multiple MIOperands inside a single one.
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bool ARMAsmParser::
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CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
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cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
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@ -1820,11 +1822,11 @@ CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
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return true;
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}
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/// CvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
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/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
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/// Needed here because the Asm Gen Matcher can't handle properly tied operands
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/// when they refer multiple MIOperands inside a single one.
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bool ARMAsmParser::
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CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
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cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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// Create a writeback register dummy placeholder.
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Inst.addOperand(MCOperand::CreateImm(0));
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@ -1834,11 +1836,11 @@ CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
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return true;
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}
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/// CvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
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/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
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/// Needed here because the Asm Gen Matcher can't handle properly tied operands
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/// when they refer multiple MIOperands inside a single one.
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bool ARMAsmParser::
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CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
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cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
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@ -1850,11 +1852,11 @@ CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
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return true;
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}
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/// CvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
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/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
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/// Needed here because the Asm Gen Matcher can't handle properly tied operands
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/// when they refer multiple MIOperands inside a single one.
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bool ARMAsmParser::
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CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
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cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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// Create a writeback register dummy placeholder.
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Inst.addOperand(MCOperand::CreateImm(0));
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@ -1870,7 +1872,7 @@ CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
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/// TODO Only preindexing and postindexing addressing are started, unindexed
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/// with option, etc are still to do.
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bool ARMAsmParser::
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ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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ARMII::AddrMode AddrMode = ARMII::AddrModeNone) {
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SMLoc S, E;
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assert(Parser.getTok().is(AsmToken::LBrac) &&
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@ -1883,7 +1885,7 @@ ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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Error(BaseRegTok.getLoc(), "register expected");
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return true;
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}
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int BaseRegNum = TryParseRegister();
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int BaseRegNum = tryParseRegister();
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if (BaseRegNum == -1) {
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Error(BaseRegTok.getLoc(), "register expected");
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return true;
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@ -1912,7 +1914,7 @@ ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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Preindexed = true;
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Parser.Lex(); // Eat comma token.
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if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
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if (parseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
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Offset, OffsetIsReg, OffsetRegNum, E))
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return true;
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const AsmToken &RBracTok = Parser.getTok();
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@ -1958,7 +1960,7 @@ ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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Parser.Lex(); // Eat comma token.
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if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
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if (parseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
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ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
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E))
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return true;
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@ -1993,7 +1995,7 @@ ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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/// +/-Rm, shift
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/// #offset
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/// we return false on success or an error otherwise.
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bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
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bool ARMAsmParser::parseMemoryOffsetReg(bool &Negative,
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bool &OffsetRegShifted,
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enum ARM_AM::ShiftOpc &ShiftType,
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const MCExpr *&ShiftAmount,
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@ -2017,7 +2019,7 @@ bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
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const AsmToken &OffsetRegTok = Parser.getTok();
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if (OffsetRegTok.is(AsmToken::Identifier)) {
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SMLoc CurLoc = OffsetRegTok.getLoc();
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OffsetRegNum = TryParseRegister();
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OffsetRegNum = tryParseRegister();
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if (OffsetRegNum != -1) {
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OffsetIsReg = true;
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||||
E = CurLoc;
|
||||
@ -2032,7 +2034,7 @@ bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
|
||||
Parser.Lex(); // Eat comma token.
|
||||
|
||||
const AsmToken &Tok = Parser.getTok();
|
||||
if (ParseShift(ShiftType, ShiftAmount, E))
|
||||
if (parseShift(ShiftType, ShiftAmount, E))
|
||||
return Error(Tok.getLoc(), "shift expected");
|
||||
OffsetRegShifted = true;
|
||||
}
|
||||
@ -2052,11 +2054,11 @@ bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
|
||||
return false;
|
||||
}
|
||||
|
||||
/// ParseShift as one of these two:
|
||||
/// parseShift as one of these two:
|
||||
/// ( lsl | lsr | asr | ror ) , # shift_amount
|
||||
/// rrx
|
||||
/// and returns true if it parses a shift otherwise it returns false.
|
||||
bool ARMAsmParser::ParseShift(ARM_AM::ShiftOpc &St,
|
||||
bool ARMAsmParser::parseShift(ARM_AM::ShiftOpc &St,
|
||||
const MCExpr *&ShiftAmount, SMLoc &E) {
|
||||
const AsmToken &Tok = Parser.getTok();
|
||||
if (Tok.isNot(AsmToken::Identifier))
|
||||
@ -2094,7 +2096,7 @@ bool ARMAsmParser::ParseShift(ARM_AM::ShiftOpc &St,
|
||||
|
||||
/// Parse a arm instruction operand. For now this parses the operand regardless
|
||||
/// of the mnemonic.
|
||||
bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
||||
bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
||||
StringRef Mnemonic) {
|
||||
SMLoc S, E;
|
||||
|
||||
@ -2114,9 +2116,9 @@ bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
||||
Error(Parser.getTok().getLoc(), "unexpected token in operand");
|
||||
return true;
|
||||
case AsmToken::Identifier: {
|
||||
if (!TryParseRegisterWithWriteBack(Operands))
|
||||
if (!tryParseRegisterWithWriteBack(Operands))
|
||||
return false;
|
||||
int Res = TryParseShiftRegister(Operands);
|
||||
int Res = tryparseShiftRegister(Operands);
|
||||
if (Res == 0) // success
|
||||
return false;
|
||||
else if (Res == -1) // irrecoverable error
|
||||
@ -2138,9 +2140,9 @@ bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
||||
return false;
|
||||
}
|
||||
case AsmToken::LBrac:
|
||||
return ParseMemory(Operands);
|
||||
return parseMemory(Operands);
|
||||
case AsmToken::LCurly:
|
||||
return ParseRegisterList(Operands);
|
||||
return parseRegisterList(Operands);
|
||||
case AsmToken::Hash:
|
||||
// #42 -> immediate.
|
||||
// TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
|
||||
@ -2157,7 +2159,7 @@ bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
||||
// FIXME: Check it's an expression prefix,
|
||||
// e.g. (FOO - :lower16:BAR) isn't legal.
|
||||
ARMMCExpr::VariantKind RefKind;
|
||||
if (ParsePrefix(RefKind))
|
||||
if (parsePrefix(RefKind))
|
||||
return true;
|
||||
|
||||
const MCExpr *SubExprVal;
|
||||
@ -2173,9 +2175,9 @@ bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
||||
}
|
||||
}
|
||||
|
||||
// ParsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
|
||||
// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
|
||||
// :lower16: and :upper16:.
|
||||
bool ARMAsmParser::ParsePrefix(ARMMCExpr::VariantKind &RefKind) {
|
||||
bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
|
||||
RefKind = ARMMCExpr::VK_ARM_None;
|
||||
|
||||
// :lower16: and :upper16: modifiers
|
||||
@ -2207,7 +2209,7 @@ bool ARMAsmParser::ParsePrefix(ARMMCExpr::VariantKind &RefKind) {
|
||||
}
|
||||
|
||||
const MCExpr *
|
||||
ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E,
|
||||
ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
|
||||
MCSymbolRefExpr::VariantKind Variant) {
|
||||
// Recurse over the given expression, rebuilding it to apply the given variant
|
||||
// to the leftmost symbol.
|
||||
@ -2234,7 +2236,7 @@ ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E,
|
||||
|
||||
case MCExpr::Binary: {
|
||||
const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
|
||||
const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant);
|
||||
const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
|
||||
const MCExpr *RHS = BE->getRHS();
|
||||
if (!LHS)
|
||||
return 0;
|
||||
@ -2251,7 +2253,7 @@ ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E,
|
||||
/// setting letters to form a canonical mnemonic and flags.
|
||||
//
|
||||
// FIXME: Would be nice to autogen this.
|
||||
StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic,
|
||||
StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
|
||||
unsigned &PredicationCode,
|
||||
bool &CarrySetting,
|
||||
unsigned &ProcessorIMod) {
|
||||
@ -2336,7 +2338,7 @@ StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic,
|
||||
//
|
||||
// FIXME: It would be nice to autogen this.
|
||||
void ARMAsmParser::
|
||||
GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
|
||||
getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
|
||||
bool &CanAcceptPredicationCode) {
|
||||
if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
|
||||
Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
|
||||
@ -2381,7 +2383,7 @@ bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
|
||||
unsigned PredicationCode;
|
||||
unsigned ProcessorIMod;
|
||||
bool CarrySetting;
|
||||
Mnemonic = SplitMnemonic(Mnemonic, PredicationCode, CarrySetting,
|
||||
Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
|
||||
ProcessorIMod);
|
||||
|
||||
Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
|
||||
@ -2397,7 +2399,7 @@ bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
|
||||
// the matcher deal with finding the right instruction or generating an
|
||||
// appropriate error.
|
||||
bool CanAcceptCarrySet, CanAcceptPredicationCode;
|
||||
GetMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
|
||||
getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
|
||||
|
||||
// If we had a carry-set on an instruction that can't do that, issue an
|
||||
// error.
|
||||
@ -2453,7 +2455,7 @@ bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
|
||||
// Read the remaining operands.
|
||||
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
||||
// Read the first operand.
|
||||
if (ParseOperand(Operands, Mnemonic)) {
|
||||
if (parseOperand(Operands, Mnemonic)) {
|
||||
Parser.EatToEndOfStatement();
|
||||
return true;
|
||||
}
|
||||
@ -2462,7 +2464,7 @@ bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
|
||||
Parser.Lex(); // Eat the comma.
|
||||
|
||||
// Parse and remember the operand.
|
||||
if (ParseOperand(Operands, Mnemonic)) {
|
||||
if (parseOperand(Operands, Mnemonic)) {
|
||||
Parser.EatToEndOfStatement();
|
||||
return true;
|
||||
}
|
||||
@ -2534,25 +2536,25 @@ MatchAndEmitInstruction(SMLoc IDLoc,
|
||||
return true;
|
||||
}
|
||||
|
||||
/// ParseDirective parses the arm specific directives
|
||||
/// parseDirective parses the arm specific directives
|
||||
bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
|
||||
StringRef IDVal = DirectiveID.getIdentifier();
|
||||
if (IDVal == ".word")
|
||||
return ParseDirectiveWord(4, DirectiveID.getLoc());
|
||||
return parseDirectiveWord(4, DirectiveID.getLoc());
|
||||
else if (IDVal == ".thumb")
|
||||
return ParseDirectiveThumb(DirectiveID.getLoc());
|
||||
return parseDirectiveThumb(DirectiveID.getLoc());
|
||||
else if (IDVal == ".thumb_func")
|
||||
return ParseDirectiveThumbFunc(DirectiveID.getLoc());
|
||||
return parseDirectiveThumbFunc(DirectiveID.getLoc());
|
||||
else if (IDVal == ".code")
|
||||
return ParseDirectiveCode(DirectiveID.getLoc());
|
||||
return parseDirectiveCode(DirectiveID.getLoc());
|
||||
else if (IDVal == ".syntax")
|
||||
return ParseDirectiveSyntax(DirectiveID.getLoc());
|
||||
return parseDirectiveSyntax(DirectiveID.getLoc());
|
||||
return true;
|
||||
}
|
||||
|
||||
/// ParseDirectiveWord
|
||||
/// parseDirectiveWord
|
||||
/// ::= .word [ expression (, expression)* ]
|
||||
bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
|
||||
bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
|
||||
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
||||
for (;;) {
|
||||
const MCExpr *Value;
|
||||
@ -2575,9 +2577,9 @@ bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
|
||||
return false;
|
||||
}
|
||||
|
||||
/// ParseDirectiveThumb
|
||||
/// parseDirectiveThumb
|
||||
/// ::= .thumb
|
||||
bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
|
||||
bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
|
||||
if (getLexer().isNot(AsmToken::EndOfStatement))
|
||||
return Error(L, "unexpected token in directive");
|
||||
Parser.Lex();
|
||||
@ -2588,9 +2590,9 @@ bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
|
||||
return false;
|
||||
}
|
||||
|
||||
/// ParseDirectiveThumbFunc
|
||||
/// parseDirectiveThumbFunc
|
||||
/// ::= .thumbfunc symbol_name
|
||||
bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
|
||||
bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
|
||||
const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
|
||||
bool isMachO = MAI.hasSubsectionsViaSymbols();
|
||||
StringRef Name;
|
||||
@ -2620,9 +2622,9 @@ bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
|
||||
return false;
|
||||
}
|
||||
|
||||
/// ParseDirectiveSyntax
|
||||
/// parseDirectiveSyntax
|
||||
/// ::= .syntax unified | divided
|
||||
bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
|
||||
bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
|
||||
const AsmToken &Tok = Parser.getTok();
|
||||
if (Tok.isNot(AsmToken::Identifier))
|
||||
return Error(L, "unexpected token in .syntax directive");
|
||||
@ -2643,9 +2645,9 @@ bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
|
||||
return false;
|
||||
}
|
||||
|
||||
/// ParseDirectiveCode
|
||||
/// parseDirectiveCode
|
||||
/// ::= .code 16 | 32
|
||||
bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
|
||||
bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
|
||||
const AsmToken &Tok = Parser.getTok();
|
||||
if (Tok.isNot(AsmToken::Integer))
|
||||
return Error(L, "unexpected token in .code directive");
|
||||
|
||||
Loading…
Reference in New Issue
Block a user