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Misc. intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27590 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -140,7 +140,8 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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// Cacheability support ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse_prefetch : GCCBuiltin<"__builtin_ia32_prefetch">,
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Intrinsic<[llvm_ptr_ty, llvm_int_ty], [IntrWriteMem]>;
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Intrinsic<[llvm_void_ty, llvm_ptr_ty,
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llvm_int_ty], [IntrWriteMem]>;
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def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">,
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Intrinsic<[llvm_void_ty, llvm_ptr_ty,
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llvm_v4f32_ty], [IntrWriteMem]>;
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@ -1516,18 +1516,18 @@ def MASKMOVDQU : PDI<0xF7, RawFrm, (ops VR128:$src, VR128:$mask),
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Imp<[EDI],[]>;
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// Prefetching loads
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def PREFETCHT0 : I<0x18, MRM1m, (ops i8mem:$src),
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"prefetcht0 $src", []>, TB,
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Requires<[HasSSE1]>;
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def PREFETCHT1 : I<0x18, MRM2m, (ops i8mem:$src),
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"prefetcht0 $src", []>, TB,
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Requires<[HasSSE1]>;
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def PREFETCHT2 : I<0x18, MRM3m, (ops i8mem:$src),
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"prefetcht0 $src", []>, TB,
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Requires<[HasSSE1]>;
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def PREFETCHTNTA : I<0x18, MRM0m, (ops i8mem:$src),
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"prefetcht0 $src", []>, TB,
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Requires<[HasSSE1]>;
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def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src),
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"prefetcht0 $src",
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[(int_x86_sse_prefetch addr:$src, 1)]>;
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def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src),
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"prefetcht1 $src",
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[(int_x86_sse_prefetch addr:$src, 2)]>;
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def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src),
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"prefetcht2 $src",
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[(int_x86_sse_prefetch addr:$src, 3)]>;
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def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src),
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"prefetchtnta $src",
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[(int_x86_sse_prefetch addr:$src, 0)]>;
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// Non-temporal stores
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def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
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@ -1546,7 +1546,7 @@ def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, R32:$src),
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// Store fence
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def SFENCE : I<0xAE, MRM7m, (ops),
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"sfence", []>, TB, Requires<[HasSSE1]>;
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"sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
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// MXCSR register
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def LDMXCSR : I<0xAE, MRM2m, (ops i32mem:$src),
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