From 136e4912806a2182a41e3011e86830a9c77160f0 Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Sat, 14 Aug 2010 03:18:29 +0000 Subject: [PATCH] T2I_rbin_irs rr variant is for disassembly only, so don't provide a pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111068 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb2.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 16b7cb41f34..1e8d80aed29 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -275,7 +275,7 @@ multiclass T2I_rbin_irs opcod, string opc, PatFrag opnode> { // register def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, rGPR:$lhs), IIC_iALUr, opc, "\t$dst, $rhs, $lhs", - [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> { + [/* For disassembly only; pattern left blank */]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-21} = opcod;