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ARM parsing for VLD1 two register all lanes, no writeback.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-11-30 18:21:25 +00:00
parent 78647434ea
commit 13af222bab
6 changed files with 31 additions and 5 deletions
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6
lib/Target/ARM/ARMExpandPseudoInsts.cpp
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@ -129,11 +129,11 @@ namespace {
}
static const NEONLdStTableEntry NEONLdStTable[] = {
{ ARM::VLD1DUPq16Pseudo, ARM::VLD1DUPq16, true, false, false, SingleSpc, 2, 4,true},
{ ARM::VLD1DUPq16Pseudo, ARM::VLD1DUPq16, true, false, false, SingleSpc, 2, 4,false},
{ ARM::VLD1DUPq16Pseudo_UPD, ARM::VLD1DUPq16_UPD, true, true, true, SingleSpc, 2, 4,true},
{ ARM::VLD1DUPq32Pseudo, ARM::VLD1DUPq32, true, false, false, SingleSpc, 2, 2,true},
{ ARM::VLD1DUPq32Pseudo, ARM::VLD1DUPq32, true, false, false, SingleSpc, 2, 2,false},
{ ARM::VLD1DUPq32Pseudo_UPD, ARM::VLD1DUPq32_UPD, true, true, true, SingleSpc, 2, 2,true},
{ ARM::VLD1DUPq8Pseudo, ARM::VLD1DUPq8, true, false, false, SingleSpc, 2, 8,true},
{ ARM::VLD1DUPq8Pseudo, ARM::VLD1DUPq8, true, false, false, SingleSpc, 2, 8,false},
{ ARM::VLD1DUPq8Pseudo_UPD, ARM::VLD1DUPq8_UPD, true, true, true, SingleSpc, 2, 8,true},
{ ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},

13
lib/Target/ARM/ARMInstrNEON.td
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@ -129,6 +129,15 @@ def VecListOneDAllLanesAsmOperand : AsmOperandClass {
def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> {
let ParserMatchClass = VecListOneDAllLanesAsmOperand;
}
// Register list of two D registers, with "all lanes" subscripting.
def VecListTwoDAllLanesAsmOperand : AsmOperandClass {
let Name = "VecListTwoDAllLanes";
let ParserMethod = "parseVectorList";
let RenderMethod = "addVecListOperands";
}
def VecListTwoDAllLanes : RegisterOperand<DPR, "printVectorListTwoAllLanes"> {
let ParserMatchClass = VecListTwoDAllLanesAsmOperand;
}
//===----------------------------------------------------------------------===//
// NEON-specific DAG Nodes.
@ -1043,9 +1052,9 @@ def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
class VLD1QDUP<bits<4> op7_4, string Dt>
: NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2),
: NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListTwoDAllLanes:$Vd),
(ins addrmode6dup:$Rn), IIC_VLD1dup,
"vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
"vld1", Dt, "$Vd, $Rn", "", []> {
let Rm = 0b1111;
let Inst{4} = Rn{4};
let DecoderMethod = "DecodeVLD1DupInstruction";

5
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -977,6 +977,11 @@ public:
return VectorList.Count == 1;
}
bool isVecListTwoDAllLanes() const {
if (Kind != k_VectorListAllLanes) return false;
return VectorList.Count == 2;
}
bool isVectorIndex8() const {
if (Kind != k_VectorIndex) return false;
return VectorIndex.Val < 8;

9
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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@ -1036,3 +1036,12 @@ void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}";
}
void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
unsigned OpNum,
raw_ostream &O) {
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
<< getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[]}";
}

2
lib/Target/ARM/InstPrinter/ARMInstPrinter.h
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@ -135,6 +135,8 @@ public:
void printVectorListFour(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
};
} // end namespace llvm

1
utils/TableGen/EDEmitter.cpp
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@ -577,6 +577,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
REG("VecListFourD");
REG("VecListTwoQ");
REG("VecListOneDAllLanes");
REG("VecListTwoDAllLanes");
IMM("i32imm");
IMM("i32imm_hilo16");