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Add XCore support for arbitrary-sized aggregate returns.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88802 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2009-11-14 19:33:35 +00:00
parent b23f3aa270
commit 13c4fabf99
3 changed files with 60 additions and 0 deletions
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11
lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -918,6 +918,17 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
// Return Value Calling Convention Implementation
//===----------------------------------------------------------------------===//
bool XCoreTargetLowering::
CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<EVT> &OutTys,
const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
SelectionDAG &DAG) {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
RVLocs, *DAG.getContext());
return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_XCore);
}
SDValue
XCoreTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,

6
lib/Target/XCore/XCoreISelLowering.h
View File

@ -159,6 +159,12 @@ namespace llvm {
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG);
virtual bool
CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<EVT> &OutTys,
const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
SelectionDAG &DAG);
};
}

43
test/CodeGen/XCore/bigstructret.ll Normal file
View File

@ -0,0 +1,43 @@
; RUN: llc < %s -march=xcore | FileCheck %s
%0 = type { i32, i32, i32, i32 }
%1 = type { i32, i32, i32, i32, i32 }
; Structs of 4 words can be returned in registers
define internal fastcc %0 @ReturnBigStruct() nounwind readnone {
entry:
%0 = insertvalue %0 zeroinitializer, i32 12, 0
%1 = insertvalue %0 %0, i32 24, 1
%2 = insertvalue %0 %1, i32 48, 2
%3 = insertvalue %0 %2, i32 24601, 3
ret %0 %3
}
; CHECK: ReturnBigStruct:
; CHECK: ldc r0, 12
; CHECK: ldc r1, 24
; CHECK: ldc r2, 48
; CHECK: ldc r3, 24601
; CHECK: retsp 0
; Structs bigger than 4 words are returned via a hidden hidden sret-parameter
define internal fastcc %1 @ReturnBigStruct2() nounwind readnone {
entry:
%0 = insertvalue %1 zeroinitializer, i32 12, 0
%1 = insertvalue %1 %0, i32 24, 1
%2 = insertvalue %1 %1, i32 48, 2
%3 = insertvalue %1 %2, i32 24601, 3
%4 = insertvalue %1 %3, i32 4321, 4
ret %1 %4
}
; CHECK: ReturnBigStruct2:
; CHECK: ldc r1, 4321
; CHECK: stw r1, r0[4]
; CHECK: ldc r1, 24601
; CHECK: stw r1, r0[3]
; CHECK: ldc r1, 48
; CHECK: stw r1, r0[2]
; CHECK: ldc r1, 24
; CHECK: stw r1, r0[1]
; CHECK: ldc r1, 12
; CHECK: stw r1, r0[0]
; CHECK: retsp 0