mirror of
https://github.com/c64scene-ar/llvm-6502.git
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AVX-512: Added SKX forms of shift instructions.
Added rotation instructions, encoding only. Added encoding tests for all these forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231916 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
e9ae43acf7
commit
13cc6f2b6e
@ -3448,15 +3448,27 @@ multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
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" ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
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let mayLoad = 1 in
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defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
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(ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode (_.LdFrag addr:$src1), (i8 imm:$src2))),
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(_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
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(i8 imm:$src2))),
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" ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
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}
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multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
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string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
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let mayLoad = 1 in
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defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
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(ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
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"$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
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(_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
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" ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V, EVEX_B;
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}
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multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
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ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
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// src2 is always 128-bit
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defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, VR128X:$src2), OpcodeStr,
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@ -3467,46 +3479,95 @@ multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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(ins _.RC:$src1, i128mem:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
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" ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V;
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" ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
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EVEX_4V;
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}
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multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
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defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512;
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ValueType SrcVT, PatFrag bc_frag,
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AVX512VLVectorVTInfo VTInfo, Predicate prd> {
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let Predicates = [prd] in
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defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
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VTInfo.info512>, EVEX_V512,
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EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
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let Predicates = [prd, HasVLX] in {
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defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
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VTInfo.info256>, EVEX_V256,
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EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
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defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
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VTInfo.info128>, EVEX_V128,
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EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
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}
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}
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multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr,
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SDNode OpNode> {
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multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
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string OpcodeStr, SDNode OpNode> {
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defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
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v16i32_info>, EVEX_CD8<32, CD8VQ>;
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avx512vl_i32_info, HasAVX512>;
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defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
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v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
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avx512vl_i64_info, HasAVX512>, VEX_W;
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defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
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avx512vl_i16_info, HasBWI>;
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}
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defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
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v16i32_info>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
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v8i64_info>, EVEX_V512,
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EVEX_CD8<64, CD8VF>, VEX_W;
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multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
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string OpcodeStr, SDNode OpNode,
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AVX512VLVectorVTInfo VTInfo> {
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let Predicates = [HasAVX512] in
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defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
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VTInfo.info512>,
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avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
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VTInfo.info512>, EVEX_V512;
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let Predicates = [HasAVX512, HasVLX] in {
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defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
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VTInfo.info256>,
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avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
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VTInfo.info256>, EVEX_V256;
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defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
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VTInfo.info128>,
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avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
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VTInfo.info128>, EVEX_V128;
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}
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}
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defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
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v16i32_info>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
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v8i64_info>, EVEX_V512,
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EVEX_CD8<64, CD8VF>, VEX_W;
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multiclass avx512_shift_rmi_w<bits<8> opcw,
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Format ImmFormR, Format ImmFormM,
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string OpcodeStr, SDNode OpNode> {
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let Predicates = [HasBWI] in
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defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
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v32i16_info>, EVEX_V512;
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let Predicates = [HasVLX, HasBWI] in {
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defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
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v16i16x_info>, EVEX_V256;
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defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
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v8i16x_info>, EVEX_V128;
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}
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}
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defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
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v16i32_info>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
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v8i64_info>, EVEX_V512,
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EVEX_CD8<64, CD8VF>, VEX_W;
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multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
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Format ImmFormR, Format ImmFormM,
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string OpcodeStr, SDNode OpNode> {
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defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
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avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
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defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
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avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
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}
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defm VPSLL : avx512_shift_types<0xF2, 0xF3, "vpsll", X86vshl>;
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defm VPSRA : avx512_shift_types<0xE2, 0xE2, "vpsra", X86vsra>;
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defm VPSRL : avx512_shift_types<0xD2, 0xD3, "vpsrl", X86vsrl>;
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defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
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avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>;
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defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
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avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>;
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defm VPSRA : avx512_shift_rmi_dq<0x72, 0x73, MRM4r, MRM4m, "vpsra", X86vsrai>,
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avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>;
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defm VPROR : avx512_shift_rmi_dq<0x72, 0x73, MRM0r, MRM0m, "vpror", rotr>;
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defm VPROL : avx512_shift_rmi_dq<0x72, 0x73, MRM1r, MRM1m, "vprol", rotl>;
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defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
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defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
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defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
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//===-------------------------------------------------------------------===//
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// Variable Bit Shifts
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@ -3518,29 +3579,71 @@ multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
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" ", SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
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let mayLoad = 1 in
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defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2))),
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" ", SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V;
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" ", SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
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EVEX_CD8<_.EltSize, CD8VF>;
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}
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multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _> {
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let mayLoad = 1 in
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defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
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"${src2}"##_.BroadcastStr##", $src1",
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"$src1, ${src2}"##_.BroadcastStr,
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(_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
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(_.ScalarLdFrag addr:$src2))))),
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" ", SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
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EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
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}
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multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
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AVX512VLVectorVTInfo _> {
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defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
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let Predicates = [HasAVX512] in
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defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
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avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
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let Predicates = [HasAVX512, HasVLX] in {
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defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
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avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
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defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
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avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
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}
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}
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multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
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SDNode OpNode> {
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defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
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avx512vl_i32_info>, EVEX_CD8<32, CD8VQ>;
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avx512vl_i32_info>;
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defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
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avx512vl_i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
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avx512vl_i64_info>, VEX_W;
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}
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defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>;
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defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>;
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defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>;
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multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
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SDNode OpNode> {
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let Predicates = [HasBWI] in
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defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
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EVEX_V512, VEX_W;
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let Predicates = [HasVLX, HasBWI] in {
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defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
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EVEX_V256, VEX_W;
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defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
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EVEX_V128, VEX_W;
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}
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}
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defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
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avx512_var_shift_w<0x12, "vpsllvw", shl>;
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defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
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avx512_var_shift_w<0x11, "vpsravw", sra>;
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defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
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avx512_var_shift_w<0x10, "vpsrlvw", srl>;
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defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
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defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
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//===----------------------------------------------------------------------===//
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// AVX-512 - MOVDDUP
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@ -4077,7 +4077,7 @@ defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
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// SSE2 - Packed Integer Logical Instructions
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//===---------------------------------------------------------------------===//
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let Predicates = [HasAVX] in {
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let Predicates = [HasAVX, NoVLX] in {
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defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
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VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
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SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
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@ -4123,7 +4123,7 @@ let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
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}
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} // Predicates = [HasAVX]
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let Predicates = [HasAVX2] in {
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let Predicates = [HasAVX2, NoVLX] in {
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defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
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VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
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SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
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@ -1747,3 +1747,264 @@
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// CHECK: vpcmpnleuw -8256(%rdx), %zmm22, %k4
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// CHECK: encoding: [0x62,0xf3,0xcd,0x40,0x3e,0xa2,0xc0,0xdf,0xff,0xff,0x06]
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vpcmpnleuw -8256(%rdx), %zmm22, %k4
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// CHECK: vpsllw %xmm24, %zmm21, %zmm24
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// CHECK: encoding: [0x62,0x01,0x55,0x40,0xf1,0xc0]
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vpsllw %xmm24, %zmm21, %zmm24
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// CHECK: vpsllw %xmm24, %zmm21, %zmm24 {%k2}
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// CHECK: encoding: [0x62,0x01,0x55,0x42,0xf1,0xc0]
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vpsllw %xmm24, %zmm21, %zmm24 {%k2}
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// CHECK: vpsllw %xmm24, %zmm21, %zmm24 {%k2} {z}
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// CHECK: encoding: [0x62,0x01,0x55,0xc2,0xf1,0xc0]
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vpsllw %xmm24, %zmm21, %zmm24 {%k2} {z}
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// CHECK: vpsllw (%rcx), %zmm21, %zmm24
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// CHECK: encoding: [0x62,0x61,0x55,0x40,0xf1,0x01]
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vpsllw (%rcx), %zmm21, %zmm24
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// CHECK: vpsllw 291(%rax,%r14,8), %zmm21, %zmm24
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// CHECK: encoding: [0x62,0x21,0x55,0x40,0xf1,0x84,0xf0,0x23,0x01,0x00,0x00]
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vpsllw 291(%rax,%r14,8), %zmm21, %zmm24
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// CHECK: vpsllw 2032(%rdx), %zmm21, %zmm24
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// CHECK: encoding: [0x62,0x61,0x55,0x40,0xf1,0x42,0x7f]
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vpsllw 2032(%rdx), %zmm21, %zmm24
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// CHECK: vpsllw 2048(%rdx), %zmm21, %zmm24
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// CHECK: encoding: [0x62,0x61,0x55,0x40,0xf1,0x82,0x00,0x08,0x00,0x00]
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vpsllw 2048(%rdx), %zmm21, %zmm24
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// CHECK: vpsllw -2048(%rdx), %zmm21, %zmm24
|
||||
// CHECK: encoding: [0x62,0x61,0x55,0x40,0xf1,0x42,0x80]
|
||||
vpsllw -2048(%rdx), %zmm21, %zmm24
|
||||
|
||||
// CHECK: vpsllw -2064(%rdx), %zmm21, %zmm24
|
||||
// CHECK: encoding: [0x62,0x61,0x55,0x40,0xf1,0x82,0xf0,0xf7,0xff,0xff]
|
||||
vpsllw -2064(%rdx), %zmm21, %zmm24
|
||||
|
||||
// CHECK: vpsraw %xmm21, %zmm27, %zmm28
|
||||
// CHECK: encoding: [0x62,0x21,0x25,0x40,0xe1,0xe5]
|
||||
vpsraw %xmm21, %zmm27, %zmm28
|
||||
|
||||
// CHECK: vpsraw %xmm21, %zmm27, %zmm28 {%k4}
|
||||
// CHECK: encoding: [0x62,0x21,0x25,0x44,0xe1,0xe5]
|
||||
vpsraw %xmm21, %zmm27, %zmm28 {%k4}
|
||||
|
||||
// CHECK: vpsraw %xmm21, %zmm27, %zmm28 {%k4} {z}
|
||||
// CHECK: encoding: [0x62,0x21,0x25,0xc4,0xe1,0xe5]
|
||||
vpsraw %xmm21, %zmm27, %zmm28 {%k4} {z}
|
||||
|
||||
// CHECK: vpsraw (%rcx), %zmm27, %zmm28
|
||||
// CHECK: encoding: [0x62,0x61,0x25,0x40,0xe1,0x21]
|
||||
vpsraw (%rcx), %zmm27, %zmm28
|
||||
|
||||
// CHECK: vpsraw 291(%rax,%r14,8), %zmm27, %zmm28
|
||||
// CHECK: encoding: [0x62,0x21,0x25,0x40,0xe1,0xa4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vpsraw 291(%rax,%r14,8), %zmm27, %zmm28
|
||||
|
||||
// CHECK: vpsraw 2032(%rdx), %zmm27, %zmm28
|
||||
// CHECK: encoding: [0x62,0x61,0x25,0x40,0xe1,0x62,0x7f]
|
||||
vpsraw 2032(%rdx), %zmm27, %zmm28
|
||||
|
||||
// CHECK: vpsraw 2048(%rdx), %zmm27, %zmm28
|
||||
// CHECK: encoding: [0x62,0x61,0x25,0x40,0xe1,0xa2,0x00,0x08,0x00,0x00]
|
||||
vpsraw 2048(%rdx), %zmm27, %zmm28
|
||||
|
||||
// CHECK: vpsraw -2048(%rdx), %zmm27, %zmm28
|
||||
// CHECK: encoding: [0x62,0x61,0x25,0x40,0xe1,0x62,0x80]
|
||||
vpsraw -2048(%rdx), %zmm27, %zmm28
|
||||
|
||||
// CHECK: vpsraw -2064(%rdx), %zmm27, %zmm28
|
||||
// CHECK: encoding: [0x62,0x61,0x25,0x40,0xe1,0xa2,0xf0,0xf7,0xff,0xff]
|
||||
vpsraw -2064(%rdx), %zmm27, %zmm28
|
||||
|
||||
// CHECK: vpsrlw %xmm22, %zmm20, %zmm23
|
||||
// CHECK: encoding: [0x62,0xa1,0x5d,0x40,0xd1,0xfe]
|
||||
vpsrlw %xmm22, %zmm20, %zmm23
|
||||
|
||||
// CHECK: vpsrlw %xmm22, %zmm20, %zmm23 {%k6}
|
||||
// CHECK: encoding: [0x62,0xa1,0x5d,0x46,0xd1,0xfe]
|
||||
vpsrlw %xmm22, %zmm20, %zmm23 {%k6}
|
||||
|
||||
// CHECK: vpsrlw %xmm22, %zmm20, %zmm23 {%k6} {z}
|
||||
// CHECK: encoding: [0x62,0xa1,0x5d,0xc6,0xd1,0xfe]
|
||||
vpsrlw %xmm22, %zmm20, %zmm23 {%k6} {z}
|
||||
|
||||
// CHECK: vpsrlw (%rcx), %zmm20, %zmm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x5d,0x40,0xd1,0x39]
|
||||
vpsrlw (%rcx), %zmm20, %zmm23
|
||||
|
||||
// CHECK: vpsrlw 291(%rax,%r14,8), %zmm20, %zmm23
|
||||
// CHECK: encoding: [0x62,0xa1,0x5d,0x40,0xd1,0xbc,0xf0,0x23,0x01,0x00,0x00]
|
||||
vpsrlw 291(%rax,%r14,8), %zmm20, %zmm23
|
||||
|
||||
// CHECK: vpsrlw 2032(%rdx), %zmm20, %zmm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x5d,0x40,0xd1,0x7a,0x7f]
|
||||
vpsrlw 2032(%rdx), %zmm20, %zmm23
|
||||
|
||||
// CHECK: vpsrlw 2048(%rdx), %zmm20, %zmm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x5d,0x40,0xd1,0xba,0x00,0x08,0x00,0x00]
|
||||
vpsrlw 2048(%rdx), %zmm20, %zmm23
|
||||
|
||||
// CHECK: vpsrlw -2048(%rdx), %zmm20, %zmm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x5d,0x40,0xd1,0x7a,0x80]
|
||||
vpsrlw -2048(%rdx), %zmm20, %zmm23
|
||||
|
||||
// CHECK: vpsrlw -2064(%rdx), %zmm20, %zmm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x5d,0x40,0xd1,0xba,0xf0,0xf7,0xff,0xff]
|
||||
vpsrlw -2064(%rdx), %zmm20, %zmm23
|
||||
|
||||
// CHECK: vpsrlw $171, %zmm26, %zmm25
|
||||
// CHECK: encoding: [0x62,0x91,0x35,0x40,0x71,0xd2,0xab]
|
||||
vpsrlw $171, %zmm26, %zmm25
|
||||
|
||||
// CHECK: vpsrlw $171, %zmm26, %zmm25 {%k6}
|
||||
// CHECK: encoding: [0x62,0x91,0x35,0x46,0x71,0xd2,0xab]
|
||||
vpsrlw $171, %zmm26, %zmm25 {%k6}
|
||||
|
||||
// CHECK: vpsrlw $171, %zmm26, %zmm25 {%k6} {z}
|
||||
// CHECK: encoding: [0x62,0x91,0x35,0xc6,0x71,0xd2,0xab]
|
||||
vpsrlw $171, %zmm26, %zmm25 {%k6} {z}
|
||||
|
||||
// CHECK: vpsrlw $123, %zmm26, %zmm25
|
||||
// CHECK: encoding: [0x62,0x91,0x35,0x40,0x71,0xd2,0x7b]
|
||||
vpsrlw $123, %zmm26, %zmm25
|
||||
|
||||
// CHECK: vpsrlw $123, (%rcx), %zmm25
|
||||
// CHECK: encoding: [0x62,0xf1,0x35,0x40,0x71,0x11,0x7b]
|
||||
vpsrlw $123, (%rcx), %zmm25
|
||||
|
||||
// CHECK: vpsrlw $123, 291(%rax,%r14,8), %zmm25
|
||||
// CHECK: encoding: [0x62,0xb1,0x35,0x40,0x71,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
|
||||
vpsrlw $123, 291(%rax,%r14,8), %zmm25
|
||||
|
||||
// CHECK: vpsrlw $123, 8128(%rdx), %zmm25
|
||||
// CHECK: encoding: [0x62,0xf1,0x35,0x40,0x71,0x52,0x7f,0x7b]
|
||||
vpsrlw $123, 8128(%rdx), %zmm25
|
||||
|
||||
// CHECK: vpsrlw $123, 8192(%rdx), %zmm25
|
||||
// CHECK: encoding: [0x62,0xf1,0x35,0x40,0x71,0x92,0x00,0x20,0x00,0x00,0x7b]
|
||||
vpsrlw $123, 8192(%rdx), %zmm25
|
||||
|
||||
// CHECK: vpsrlw $123, -8192(%rdx), %zmm25
|
||||
// CHECK: encoding: [0x62,0xf1,0x35,0x40,0x71,0x52,0x80,0x7b]
|
||||
vpsrlw $123, -8192(%rdx), %zmm25
|
||||
|
||||
// CHECK: vpsrlw $123, -8256(%rdx), %zmm25
|
||||
// CHECK: encoding: [0x62,0xf1,0x35,0x40,0x71,0x92,0xc0,0xdf,0xff,0xff,0x7b]
|
||||
vpsrlw $123, -8256(%rdx), %zmm25
|
||||
|
||||
// CHECK: vpsraw $171, %zmm29, %zmm28
|
||||
// CHECK: encoding: [0x62,0x91,0x1d,0x40,0x71,0xe5,0xab]
|
||||
vpsraw $171, %zmm29, %zmm28
|
||||
|
||||
// CHECK: vpsraw $171, %zmm29, %zmm28 {%k4}
|
||||
// CHECK: encoding: [0x62,0x91,0x1d,0x44,0x71,0xe5,0xab]
|
||||
vpsraw $171, %zmm29, %zmm28 {%k4}
|
||||
|
||||
// CHECK: vpsraw $171, %zmm29, %zmm28 {%k4} {z}
|
||||
// CHECK: encoding: [0x62,0x91,0x1d,0xc4,0x71,0xe5,0xab]
|
||||
vpsraw $171, %zmm29, %zmm28 {%k4} {z}
|
||||
|
||||
// CHECK: vpsraw $123, %zmm29, %zmm28
|
||||
// CHECK: encoding: [0x62,0x91,0x1d,0x40,0x71,0xe5,0x7b]
|
||||
vpsraw $123, %zmm29, %zmm28
|
||||
|
||||
// CHECK: vpsraw $123, (%rcx), %zmm28
|
||||
// CHECK: encoding: [0x62,0xf1,0x1d,0x40,0x71,0x21,0x7b]
|
||||
vpsraw $123, (%rcx), %zmm28
|
||||
|
||||
// CHECK: vpsraw $123, 291(%rax,%r14,8), %zmm28
|
||||
// CHECK: encoding: [0x62,0xb1,0x1d,0x40,0x71,0xa4,0xf0,0x23,0x01,0x00,0x00,0x7b]
|
||||
vpsraw $123, 291(%rax,%r14,8), %zmm28
|
||||
|
||||
// CHECK: vpsraw $123, 8128(%rdx), %zmm28
|
||||
// CHECK: encoding: [0x62,0xf1,0x1d,0x40,0x71,0x62,0x7f,0x7b]
|
||||
vpsraw $123, 8128(%rdx), %zmm28
|
||||
|
||||
// CHECK: vpsraw $123, 8192(%rdx), %zmm28
|
||||
// CHECK: encoding: [0x62,0xf1,0x1d,0x40,0x71,0xa2,0x00,0x20,0x00,0x00,0x7b]
|
||||
vpsraw $123, 8192(%rdx), %zmm28
|
||||
|
||||
// CHECK: vpsraw $123, -8192(%rdx), %zmm28
|
||||
// CHECK: encoding: [0x62,0xf1,0x1d,0x40,0x71,0x62,0x80,0x7b]
|
||||
vpsraw $123, -8192(%rdx), %zmm28
|
||||
|
||||
// CHECK: vpsraw $123, -8256(%rdx), %zmm28
|
||||
// CHECK: encoding: [0x62,0xf1,0x1d,0x40,0x71,0xa2,0xc0,0xdf,0xff,0xff,0x7b]
|
||||
vpsraw $123, -8256(%rdx), %zmm28
|
||||
|
||||
// CHECK: vpsrlvw %zmm21, %zmm18, %zmm17
|
||||
// CHECK: encoding: [0x62,0xa2,0xed,0x40,0x10,0xcd]
|
||||
vpsrlvw %zmm21, %zmm18, %zmm17
|
||||
|
||||
// CHECK: vpsrlvw %zmm21, %zmm18, %zmm17 {%k6}
|
||||
// CHECK: encoding: [0x62,0xa2,0xed,0x46,0x10,0xcd]
|
||||
vpsrlvw %zmm21, %zmm18, %zmm17 {%k6}
|
||||
|
||||
// CHECK: vpsrlvw %zmm21, %zmm18, %zmm17 {%k6} {z}
|
||||
// CHECK: encoding: [0x62,0xa2,0xed,0xc6,0x10,0xcd]
|
||||
vpsrlvw %zmm21, %zmm18, %zmm17 {%k6} {z}
|
||||
|
||||
// CHECK: vpsrlvw (%rcx), %zmm18, %zmm17
|
||||
// CHECK: encoding: [0x62,0xe2,0xed,0x40,0x10,0x09]
|
||||
vpsrlvw (%rcx), %zmm18, %zmm17
|
||||
|
||||
// CHECK: vpsrlvw 291(%rax,%r14,8), %zmm18, %zmm17
|
||||
// CHECK: encoding: [0x62,0xa2,0xed,0x40,0x10,0x8c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vpsrlvw 291(%rax,%r14,8), %zmm18, %zmm17
|
||||
|
||||
// CHECK: vpsrlvw 8128(%rdx), %zmm18, %zmm17
|
||||
// CHECK: encoding: [0x62,0xe2,0xed,0x40,0x10,0x4a,0x7f]
|
||||
vpsrlvw 8128(%rdx), %zmm18, %zmm17
|
||||
|
||||
// CHECK: vpsrlvw 8192(%rdx), %zmm18, %zmm17
|
||||
// CHECK: encoding: [0x62,0xe2,0xed,0x40,0x10,0x8a,0x00,0x20,0x00,0x00]
|
||||
vpsrlvw 8192(%rdx), %zmm18, %zmm17
|
||||
|
||||
// CHECK: vpsrlvw -8192(%rdx), %zmm18, %zmm17
|
||||
// CHECK: encoding: [0x62,0xe2,0xed,0x40,0x10,0x4a,0x80]
|
||||
vpsrlvw -8192(%rdx), %zmm18, %zmm17
|
||||
|
||||
// CHECK: vpsrlvw -8256(%rdx), %zmm18, %zmm17
|
||||
// CHECK: encoding: [0x62,0xe2,0xed,0x40,0x10,0x8a,0xc0,0xdf,0xff,0xff]
|
||||
vpsrlvw -8256(%rdx), %zmm18, %zmm17
|
||||
|
||||
// CHECK: vpsravw %zmm20, %zmm29, %zmm19
|
||||
// CHECK: encoding: [0x62,0xa2,0x95,0x40,0x11,0xdc]
|
||||
vpsravw %zmm20, %zmm29, %zmm19
|
||||
|
||||
// CHECK: vpsravw %zmm20, %zmm29, %zmm19 {%k7}
|
||||
// CHECK: encoding: [0x62,0xa2,0x95,0x47,0x11,0xdc]
|
||||
vpsravw %zmm20, %zmm29, %zmm19 {%k7}
|
||||
|
||||
// CHECK: vpsravw %zmm20, %zmm29, %zmm19 {%k7} {z}
|
||||
// CHECK: encoding: [0x62,0xa2,0x95,0xc7,0x11,0xdc]
|
||||
vpsravw %zmm20, %zmm29, %zmm19 {%k7} {z}
|
||||
|
||||
// CHECK: vpsravw (%rcx), %zmm29, %zmm19
|
||||
// CHECK: encoding: [0x62,0xe2,0x95,0x40,0x11,0x19]
|
||||
vpsravw (%rcx), %zmm29, %zmm19
|
||||
|
||||
// CHECK: vpsravw 291(%rax,%r14,8), %zmm29, %zmm19
|
||||
// CHECK: encoding: [0x62,0xa2,0x95,0x40,0x11,0x9c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vpsravw 291(%rax,%r14,8), %zmm29, %zmm19
|
||||
|
||||
// CHECK: vpsravw 8128(%rdx), %zmm29, %zmm19
|
||||
// CHECK: encoding: [0x62,0xe2,0x95,0x40,0x11,0x5a,0x7f]
|
||||
vpsravw 8128(%rdx), %zmm29, %zmm19
|
||||
|
||||
// CHECK: vpsravw 8192(%rdx), %zmm29, %zmm19
|
||||
// CHECK: encoding: [0x62,0xe2,0x95,0x40,0x11,0x9a,0x00,0x20,0x00,0x00]
|
||||
vpsravw 8192(%rdx), %zmm29, %zmm19
|
||||
|
||||
// CHECK: vpsravw -8192(%rdx), %zmm29, %zmm19
|
||||
// CHECK: encoding: [0x62,0xe2,0x95,0x40,0x11,0x5a,0x80]
|
||||
vpsravw -8192(%rdx), %zmm29, %zmm19
|
||||
|
||||
// CHECK: vpsravw -8256(%rdx), %zmm29, %zmm19
|
||||
// CHECK: encoding: [0x62,0xe2,0x95,0x40,0x11,0x9a,0xc0,0xdf,0xff,0xff]
|
||||
vpsravw -8256(%rdx), %zmm29, %zmm19
|
||||
|
||||
|
||||
@ -1783,3 +1783,523 @@
|
||||
// CHECK: vmovdqu16 %ymm29, -4128(%rdx)
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x28,0x7f,0xaa,0xe0,0xef,0xff,0xff]
|
||||
vmovdqu16 %ymm29, -4128(%rdx)
|
||||
|
||||
// CHECK: vpsllw %xmm26, %xmm23, %xmm19
|
||||
// CHECK: encoding: [0x62,0x81,0x45,0x00,0xf1,0xda]
|
||||
vpsllw %xmm26, %xmm23, %xmm19
|
||||
|
||||
// CHECK: vpsllw %xmm26, %xmm23, %xmm19 {%k7}
|
||||
// CHECK: encoding: [0x62,0x81,0x45,0x07,0xf1,0xda]
|
||||
vpsllw %xmm26, %xmm23, %xmm19 {%k7}
|
||||
|
||||
// CHECK: vpsllw %xmm26, %xmm23, %xmm19 {%k7} {z}
|
||||
// CHECK: encoding: [0x62,0x81,0x45,0x87,0xf1,0xda]
|
||||
vpsllw %xmm26, %xmm23, %xmm19 {%k7} {z}
|
||||
|
||||
// CHECK: vpsllw (%rcx), %xmm23, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x45,0x00,0xf1,0x19]
|
||||
vpsllw (%rcx), %xmm23, %xmm19
|
||||
|
||||
// CHECK: vpsllw 291(%rax,%r14,8), %xmm23, %xmm19
|
||||
// CHECK: encoding: [0x62,0xa1,0x45,0x00,0xf1,0x9c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vpsllw 291(%rax,%r14,8), %xmm23, %xmm19
|
||||
|
||||
// CHECK: vpsllw 2032(%rdx), %xmm23, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x45,0x00,0xf1,0x5a,0x7f]
|
||||
vpsllw 2032(%rdx), %xmm23, %xmm19
|
||||
|
||||
// CHECK: vpsllw 2048(%rdx), %xmm23, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x45,0x00,0xf1,0x9a,0x00,0x08,0x00,0x00]
|
||||
vpsllw 2048(%rdx), %xmm23, %xmm19
|
||||
|
||||
// CHECK: vpsllw -2048(%rdx), %xmm23, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x45,0x00,0xf1,0x5a,0x80]
|
||||
vpsllw -2048(%rdx), %xmm23, %xmm19
|
||||
|
||||
// CHECK: vpsllw -2064(%rdx), %xmm23, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x45,0x00,0xf1,0x9a,0xf0,0xf7,0xff,0xff]
|
||||
vpsllw -2064(%rdx), %xmm23, %xmm19
|
||||
|
||||
// CHECK: vpsllw %xmm26, %ymm21, %ymm20
|
||||
// CHECK: encoding: [0x62,0x81,0x55,0x20,0xf1,0xe2]
|
||||
vpsllw %xmm26, %ymm21, %ymm20
|
||||
|
||||
// CHECK: vpsllw %xmm26, %ymm21, %ymm20 {%k7}
|
||||
// CHECK: encoding: [0x62,0x81,0x55,0x27,0xf1,0xe2]
|
||||
vpsllw %xmm26, %ymm21, %ymm20 {%k7}
|
||||
|
||||
// CHECK: vpsllw %xmm26, %ymm21, %ymm20 {%k7} {z}
|
||||
// CHECK: encoding: [0x62,0x81,0x55,0xa7,0xf1,0xe2]
|
||||
vpsllw %xmm26, %ymm21, %ymm20 {%k7} {z}
|
||||
|
||||
// CHECK: vpsllw (%rcx), %ymm21, %ymm20
|
||||
// CHECK: encoding: [0x62,0xe1,0x55,0x20,0xf1,0x21]
|
||||
vpsllw (%rcx), %ymm21, %ymm20
|
||||
|
||||
// CHECK: vpsllw 291(%rax,%r14,8), %ymm21, %ymm20
|
||||
// CHECK: encoding: [0x62,0xa1,0x55,0x20,0xf1,0xa4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vpsllw 291(%rax,%r14,8), %ymm21, %ymm20
|
||||
|
||||
// CHECK: vpsllw 2032(%rdx), %ymm21, %ymm20
|
||||
// CHECK: encoding: [0x62,0xe1,0x55,0x20,0xf1,0x62,0x7f]
|
||||
vpsllw 2032(%rdx), %ymm21, %ymm20
|
||||
|
||||
// CHECK: vpsllw 2048(%rdx), %ymm21, %ymm20
|
||||
// CHECK: encoding: [0x62,0xe1,0x55,0x20,0xf1,0xa2,0x00,0x08,0x00,0x00]
|
||||
vpsllw 2048(%rdx), %ymm21, %ymm20
|
||||
|
||||
// CHECK: vpsllw -2048(%rdx), %ymm21, %ymm20
|
||||
// CHECK: encoding: [0x62,0xe1,0x55,0x20,0xf1,0x62,0x80]
|
||||
vpsllw -2048(%rdx), %ymm21, %ymm20
|
||||
|
||||
// CHECK: vpsllw -2064(%rdx), %ymm21, %ymm20
|
||||
// CHECK: encoding: [0x62,0xe1,0x55,0x20,0xf1,0xa2,0xf0,0xf7,0xff,0xff]
|
||||
vpsllw -2064(%rdx), %ymm21, %ymm20
|
||||
|
||||
// CHECK: vpsraw %xmm28, %xmm28, %xmm17
|
||||
// CHECK: encoding: [0x62,0x81,0x1d,0x00,0xe1,0xcc]
|
||||
vpsraw %xmm28, %xmm28, %xmm17
|
||||
|
||||
// CHECK: vpsraw %xmm28, %xmm28, %xmm17 {%k1}
|
||||
// CHECK: encoding: [0x62,0x81,0x1d,0x01,0xe1,0xcc]
|
||||
vpsraw %xmm28, %xmm28, %xmm17 {%k1}
|
||||
|
||||
// CHECK: vpsraw %xmm28, %xmm28, %xmm17 {%k1} {z}
|
||||
// CHECK: encoding: [0x62,0x81,0x1d,0x81,0xe1,0xcc]
|
||||
vpsraw %xmm28, %xmm28, %xmm17 {%k1} {z}
|
||||
|
||||
// CHECK: vpsraw (%rcx), %xmm28, %xmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0x1d,0x00,0xe1,0x09]
|
||||
vpsraw (%rcx), %xmm28, %xmm17
|
||||
|
||||
// CHECK: vpsraw 291(%rax,%r14,8), %xmm28, %xmm17
|
||||
// CHECK: encoding: [0x62,0xa1,0x1d,0x00,0xe1,0x8c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vpsraw 291(%rax,%r14,8), %xmm28, %xmm17
|
||||
|
||||
// CHECK: vpsraw 2032(%rdx), %xmm28, %xmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0x1d,0x00,0xe1,0x4a,0x7f]
|
||||
vpsraw 2032(%rdx), %xmm28, %xmm17
|
||||
|
||||
// CHECK: vpsraw 2048(%rdx), %xmm28, %xmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0x1d,0x00,0xe1,0x8a,0x00,0x08,0x00,0x00]
|
||||
vpsraw 2048(%rdx), %xmm28, %xmm17
|
||||
|
||||
// CHECK: vpsraw -2048(%rdx), %xmm28, %xmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0x1d,0x00,0xe1,0x4a,0x80]
|
||||
vpsraw -2048(%rdx), %xmm28, %xmm17
|
||||
|
||||
// CHECK: vpsraw -2064(%rdx), %xmm28, %xmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0x1d,0x00,0xe1,0x8a,0xf0,0xf7,0xff,0xff]
|
||||
vpsraw -2064(%rdx), %xmm28, %xmm17
|
||||
|
||||
// CHECK: vpsraw %xmm19, %ymm26, %ymm18
|
||||
// CHECK: encoding: [0x62,0xa1,0x2d,0x20,0xe1,0xd3]
|
||||
vpsraw %xmm19, %ymm26, %ymm18
|
||||
|
||||
// CHECK: vpsraw %xmm19, %ymm26, %ymm18 {%k7}
|
||||
// CHECK: encoding: [0x62,0xa1,0x2d,0x27,0xe1,0xd3]
|
||||
vpsraw %xmm19, %ymm26, %ymm18 {%k7}
|
||||
|
||||
// CHECK: vpsraw %xmm19, %ymm26, %ymm18 {%k7} {z}
|
||||
// CHECK: encoding: [0x62,0xa1,0x2d,0xa7,0xe1,0xd3]
|
||||
vpsraw %xmm19, %ymm26, %ymm18 {%k7} {z}
|
||||
|
||||
// CHECK: vpsraw (%rcx), %ymm26, %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0x2d,0x20,0xe1,0x11]
|
||||
vpsraw (%rcx), %ymm26, %ymm18
|
||||
|
||||
// CHECK: vpsraw 291(%rax,%r14,8), %ymm26, %ymm18
|
||||
// CHECK: encoding: [0x62,0xa1,0x2d,0x20,0xe1,0x94,0xf0,0x23,0x01,0x00,0x00]
|
||||
vpsraw 291(%rax,%r14,8), %ymm26, %ymm18
|
||||
|
||||
// CHECK: vpsraw 2032(%rdx), %ymm26, %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0x2d,0x20,0xe1,0x52,0x7f]
|
||||
vpsraw 2032(%rdx), %ymm26, %ymm18
|
||||
|
||||
// CHECK: vpsraw 2048(%rdx), %ymm26, %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0x2d,0x20,0xe1,0x92,0x00,0x08,0x00,0x00]
|
||||
vpsraw 2048(%rdx), %ymm26, %ymm18
|
||||
|
||||
// CHECK: vpsraw -2048(%rdx), %ymm26, %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0x2d,0x20,0xe1,0x52,0x80]
|
||||
vpsraw -2048(%rdx), %ymm26, %ymm18
|
||||
|
||||
// CHECK: vpsraw -2064(%rdx), %ymm26, %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0x2d,0x20,0xe1,0x92,0xf0,0xf7,0xff,0xff]
|
||||
vpsraw -2064(%rdx), %ymm26, %ymm18
|
||||
|
||||
// CHECK: vpsrlw %xmm27, %xmm29, %xmm30
|
||||
// CHECK: encoding: [0x62,0x01,0x15,0x00,0xd1,0xf3]
|
||||
vpsrlw %xmm27, %xmm29, %xmm30
|
||||
|
||||
// CHECK: vpsrlw %xmm27, %xmm29, %xmm30 {%k1}
|
||||
// CHECK: encoding: [0x62,0x01,0x15,0x01,0xd1,0xf3]
|
||||
vpsrlw %xmm27, %xmm29, %xmm30 {%k1}
|
||||
|
||||
// CHECK: vpsrlw %xmm27, %xmm29, %xmm30 {%k1} {z}
|
||||
// CHECK: encoding: [0x62,0x01,0x15,0x81,0xd1,0xf3]
|
||||
vpsrlw %xmm27, %xmm29, %xmm30 {%k1} {z}
|
||||
|
||||
// CHECK: vpsrlw (%rcx), %xmm29, %xmm30
|
||||
// CHECK: encoding: [0x62,0x61,0x15,0x00,0xd1,0x31]
|
||||
vpsrlw (%rcx), %xmm29, %xmm30
|
||||
|
||||
// CHECK: vpsrlw 291(%rax,%r14,8), %xmm29, %xmm30
|
||||
// CHECK: encoding: [0x62,0x21,0x15,0x00,0xd1,0xb4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vpsrlw 291(%rax,%r14,8), %xmm29, %xmm30
|
||||
|
||||
// CHECK: vpsrlw 2032(%rdx), %xmm29, %xmm30
|
||||
// CHECK: encoding: [0x62,0x61,0x15,0x00,0xd1,0x72,0x7f]
|
||||
vpsrlw 2032(%rdx), %xmm29, %xmm30
|
||||
|
||||
// CHECK: vpsrlw 2048(%rdx), %xmm29, %xmm30
|
||||
// CHECK: encoding: [0x62,0x61,0x15,0x00,0xd1,0xb2,0x00,0x08,0x00,0x00]
|
||||
vpsrlw 2048(%rdx), %xmm29, %xmm30
|
||||
|
||||
// CHECK: vpsrlw -2048(%rdx), %xmm29, %xmm30
|
||||
// CHECK: encoding: [0x62,0x61,0x15,0x00,0xd1,0x72,0x80]
|
||||
vpsrlw -2048(%rdx), %xmm29, %xmm30
|
||||
|
||||
// CHECK: vpsrlw -2064(%rdx), %xmm29, %xmm30
|
||||
// CHECK: encoding: [0x62,0x61,0x15,0x00,0xd1,0xb2,0xf0,0xf7,0xff,0xff]
|
||||
vpsrlw -2064(%rdx), %xmm29, %xmm30
|
||||
|
||||
// CHECK: vpsrlw %xmm27, %ymm18, %ymm28
|
||||
// CHECK: encoding: [0x62,0x01,0x6d,0x20,0xd1,0xe3]
|
||||
vpsrlw %xmm27, %ymm18, %ymm28
|
||||
|
||||
// CHECK: vpsrlw %xmm27, %ymm18, %ymm28 {%k2}
|
||||
// CHECK: encoding: [0x62,0x01,0x6d,0x22,0xd1,0xe3]
|
||||
vpsrlw %xmm27, %ymm18, %ymm28 {%k2}
|
||||
|
||||
// CHECK: vpsrlw %xmm27, %ymm18, %ymm28 {%k2} {z}
|
||||
// CHECK: encoding: [0x62,0x01,0x6d,0xa2,0xd1,0xe3]
|
||||
vpsrlw %xmm27, %ymm18, %ymm28 {%k2} {z}
|
||||
|
||||
// CHECK: vpsrlw (%rcx), %ymm18, %ymm28
|
||||
// CHECK: encoding: [0x62,0x61,0x6d,0x20,0xd1,0x21]
|
||||
vpsrlw (%rcx), %ymm18, %ymm28
|
||||
|
||||
// CHECK: vpsrlw 291(%rax,%r14,8), %ymm18, %ymm28
|
||||
// CHECK: encoding: [0x62,0x21,0x6d,0x20,0xd1,0xa4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vpsrlw 291(%rax,%r14,8), %ymm18, %ymm28
|
||||
|
||||
// CHECK: vpsrlw 2032(%rdx), %ymm18, %ymm28
|
||||
// CHECK: encoding: [0x62,0x61,0x6d,0x20,0xd1,0x62,0x7f]
|
||||
vpsrlw 2032(%rdx), %ymm18, %ymm28
|
||||
|
||||
// CHECK: vpsrlw 2048(%rdx), %ymm18, %ymm28
|
||||
// CHECK: encoding: [0x62,0x61,0x6d,0x20,0xd1,0xa2,0x00,0x08,0x00,0x00]
|
||||
vpsrlw 2048(%rdx), %ymm18, %ymm28
|
||||
|
||||
// CHECK: vpsrlw -2048(%rdx), %ymm18, %ymm28
|
||||
// CHECK: encoding: [0x62,0x61,0x6d,0x20,0xd1,0x62,0x80]
|
||||
vpsrlw -2048(%rdx), %ymm18, %ymm28
|
||||
|
||||
// CHECK: vpsrlw -2064(%rdx), %ymm18, %ymm28
|
||||
// CHECK: encoding: [0x62,0x61,0x6d,0x20,0xd1,0xa2,0xf0,0xf7,0xff,0xff]
|
||||
vpsrlw -2064(%rdx), %ymm18, %ymm28
|
||||
|
||||
// CHECK: vpsrlw $171, %xmm21, %xmm22
|
||||
// CHECK: encoding: [0x62,0xb1,0x4d,0x00,0x71,0xd5,0xab]
|
||||
vpsrlw $171, %xmm21, %xmm22
|
||||
|
||||
// CHECK: vpsrlw $171, %xmm21, %xmm22 {%k7}
|
||||
// CHECK: encoding: [0x62,0xb1,0x4d,0x07,0x71,0xd5,0xab]
|
||||
vpsrlw $171, %xmm21, %xmm22 {%k7}
|
||||
|
||||
// CHECK: vpsrlw $171, %xmm21, %xmm22 {%k7} {z}
|
||||
// CHECK: encoding: [0x62,0xb1,0x4d,0x87,0x71,0xd5,0xab]
|
||||
vpsrlw $171, %xmm21, %xmm22 {%k7} {z}
|
||||
|
||||
// CHECK: vpsrlw $123, %xmm21, %xmm22
|
||||
// CHECK: encoding: [0x62,0xb1,0x4d,0x00,0x71,0xd5,0x7b]
|
||||
vpsrlw $123, %xmm21, %xmm22
|
||||
|
||||
// CHECK: vpsrlw $123, (%rcx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xf1,0x4d,0x00,0x71,0x11,0x7b]
|
||||
vpsrlw $123, (%rcx), %xmm22
|
||||
|
||||
// CHECK: vpsrlw $123, 291(%rax,%r14,8), %xmm22
|
||||
// CHECK: encoding: [0x62,0xb1,0x4d,0x00,0x71,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
|
||||
vpsrlw $123, 291(%rax,%r14,8), %xmm22
|
||||
|
||||
// CHECK: vpsrlw $123, 2032(%rdx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xf1,0x4d,0x00,0x71,0x52,0x7f,0x7b]
|
||||
vpsrlw $123, 2032(%rdx), %xmm22
|
||||
|
||||
// CHECK: vpsrlw $123, 2048(%rdx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xf1,0x4d,0x00,0x71,0x92,0x00,0x08,0x00,0x00,0x7b]
|
||||
vpsrlw $123, 2048(%rdx), %xmm22
|
||||
|
||||
// CHECK: vpsrlw $123, -2048(%rdx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xf1,0x4d,0x00,0x71,0x52,0x80,0x7b]
|
||||
vpsrlw $123, -2048(%rdx), %xmm22
|
||||
|
||||
// CHECK: vpsrlw $123, -2064(%rdx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xf1,0x4d,0x00,0x71,0x92,0xf0,0xf7,0xff,0xff,0x7b]
|
||||
vpsrlw $123, -2064(%rdx), %xmm22
|
||||
|
||||
// CHECK: vpsrlw $171, %ymm19, %ymm27
|
||||
// CHECK: encoding: [0x62,0xb1,0x25,0x20,0x71,0xd3,0xab]
|
||||
vpsrlw $171, %ymm19, %ymm27
|
||||
|
||||
// CHECK: vpsrlw $171, %ymm19, %ymm27 {%k3}
|
||||
// CHECK: encoding: [0x62,0xb1,0x25,0x23,0x71,0xd3,0xab]
|
||||
vpsrlw $171, %ymm19, %ymm27 {%k3}
|
||||
|
||||
// CHECK: vpsrlw $171, %ymm19, %ymm27 {%k3} {z}
|
||||
// CHECK: encoding: [0x62,0xb1,0x25,0xa3,0x71,0xd3,0xab]
|
||||
vpsrlw $171, %ymm19, %ymm27 {%k3} {z}
|
||||
|
||||
// CHECK: vpsrlw $123, %ymm19, %ymm27
|
||||
// CHECK: encoding: [0x62,0xb1,0x25,0x20,0x71,0xd3,0x7b]
|
||||
vpsrlw $123, %ymm19, %ymm27
|
||||
|
||||
// CHECK: vpsrlw $123, (%rcx), %ymm27
|
||||
// CHECK: encoding: [0x62,0xf1,0x25,0x20,0x71,0x11,0x7b]
|
||||
vpsrlw $123, (%rcx), %ymm27
|
||||
|
||||
// CHECK: vpsrlw $123, 291(%rax,%r14,8), %ymm27
|
||||
// CHECK: encoding: [0x62,0xb1,0x25,0x20,0x71,0x94,0xf0,0x23,0x01,0x00,0x00,0x7b]
|
||||
vpsrlw $123, 291(%rax,%r14,8), %ymm27
|
||||
|
||||
// CHECK: vpsrlw $123, 4064(%rdx), %ymm27
|
||||
// CHECK: encoding: [0x62,0xf1,0x25,0x20,0x71,0x52,0x7f,0x7b]
|
||||
vpsrlw $123, 4064(%rdx), %ymm27
|
||||
|
||||
// CHECK: vpsrlw $123, 4096(%rdx), %ymm27
|
||||
// CHECK: encoding: [0x62,0xf1,0x25,0x20,0x71,0x92,0x00,0x10,0x00,0x00,0x7b]
|
||||
vpsrlw $123, 4096(%rdx), %ymm27
|
||||
|
||||
// CHECK: vpsrlw $123, -4096(%rdx), %ymm27
|
||||
// CHECK: encoding: [0x62,0xf1,0x25,0x20,0x71,0x52,0x80,0x7b]
|
||||
vpsrlw $123, -4096(%rdx), %ymm27
|
||||
|
||||
// CHECK: vpsrlw $123, -4128(%rdx), %ymm27
|
||||
// CHECK: encoding: [0x62,0xf1,0x25,0x20,0x71,0x92,0xe0,0xef,0xff,0xff,0x7b]
|
||||
vpsrlw $123, -4128(%rdx), %ymm27
|
||||
|
||||
// CHECK: vpsraw $171, %xmm22, %xmm22
|
||||
// CHECK: encoding: [0x62,0xb1,0x4d,0x00,0x71,0xe6,0xab]
|
||||
vpsraw $171, %xmm22, %xmm22
|
||||
|
||||
// CHECK: vpsraw $171, %xmm22, %xmm22 {%k4}
|
||||
// CHECK: encoding: [0x62,0xb1,0x4d,0x04,0x71,0xe6,0xab]
|
||||
vpsraw $171, %xmm22, %xmm22 {%k4}
|
||||
|
||||
// CHECK: vpsraw $171, %xmm22, %xmm22 {%k4} {z}
|
||||
// CHECK: encoding: [0x62,0xb1,0x4d,0x84,0x71,0xe6,0xab]
|
||||
vpsraw $171, %xmm22, %xmm22 {%k4} {z}
|
||||
|
||||
// CHECK: vpsraw $123, %xmm22, %xmm22
|
||||
// CHECK: encoding: [0x62,0xb1,0x4d,0x00,0x71,0xe6,0x7b]
|
||||
vpsraw $123, %xmm22, %xmm22
|
||||
|
||||
// CHECK: vpsraw $123, (%rcx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xf1,0x4d,0x00,0x71,0x21,0x7b]
|
||||
vpsraw $123, (%rcx), %xmm22
|
||||
|
||||
// CHECK: vpsraw $123, 291(%rax,%r14,8), %xmm22
|
||||
// CHECK: encoding: [0x62,0xb1,0x4d,0x00,0x71,0xa4,0xf0,0x23,0x01,0x00,0x00,0x7b]
|
||||
vpsraw $123, 291(%rax,%r14,8), %xmm22
|
||||
|
||||
// CHECK: vpsraw $123, 2032(%rdx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xf1,0x4d,0x00,0x71,0x62,0x7f,0x7b]
|
||||
vpsraw $123, 2032(%rdx), %xmm22
|
||||
|
||||
// CHECK: vpsraw $123, 2048(%rdx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xf1,0x4d,0x00,0x71,0xa2,0x00,0x08,0x00,0x00,0x7b]
|
||||
vpsraw $123, 2048(%rdx), %xmm22
|
||||
|
||||
// CHECK: vpsraw $123, -2048(%rdx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xf1,0x4d,0x00,0x71,0x62,0x80,0x7b]
|
||||
vpsraw $123, -2048(%rdx), %xmm22
|
||||
|
||||
// CHECK: vpsraw $123, -2064(%rdx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xf1,0x4d,0x00,0x71,0xa2,0xf0,0xf7,0xff,0xff,0x7b]
|
||||
vpsraw $123, -2064(%rdx), %xmm22
|
||||
|
||||
// CHECK: vpsraw $171, %ymm22, %ymm19
|
||||
// CHECK: encoding: [0x62,0xb1,0x65,0x20,0x71,0xe6,0xab]
|
||||
vpsraw $171, %ymm22, %ymm19
|
||||
|
||||
// CHECK: vpsraw $171, %ymm22, %ymm19 {%k7}
|
||||
// CHECK: encoding: [0x62,0xb1,0x65,0x27,0x71,0xe6,0xab]
|
||||
vpsraw $171, %ymm22, %ymm19 {%k7}
|
||||
|
||||
// CHECK: vpsraw $171, %ymm22, %ymm19 {%k7} {z}
|
||||
// CHECK: encoding: [0x62,0xb1,0x65,0xa7,0x71,0xe6,0xab]
|
||||
vpsraw $171, %ymm22, %ymm19 {%k7} {z}
|
||||
|
||||
// CHECK: vpsraw $123, %ymm22, %ymm19
|
||||
// CHECK: encoding: [0x62,0xb1,0x65,0x20,0x71,0xe6,0x7b]
|
||||
vpsraw $123, %ymm22, %ymm19
|
||||
|
||||
// CHECK: vpsraw $123, (%rcx), %ymm19
|
||||
// CHECK: encoding: [0x62,0xf1,0x65,0x20,0x71,0x21,0x7b]
|
||||
vpsraw $123, (%rcx), %ymm19
|
||||
|
||||
// CHECK: vpsraw $123, 291(%rax,%r14,8), %ymm19
|
||||
// CHECK: encoding: [0x62,0xb1,0x65,0x20,0x71,0xa4,0xf0,0x23,0x01,0x00,0x00,0x7b]
|
||||
vpsraw $123, 291(%rax,%r14,8), %ymm19
|
||||
|
||||
// CHECK: vpsraw $123, 4064(%rdx), %ymm19
|
||||
// CHECK: encoding: [0x62,0xf1,0x65,0x20,0x71,0x62,0x7f,0x7b]
|
||||
vpsraw $123, 4064(%rdx), %ymm19
|
||||
|
||||
// CHECK: vpsraw $123, 4096(%rdx), %ymm19
|
||||
// CHECK: encoding: [0x62,0xf1,0x65,0x20,0x71,0xa2,0x00,0x10,0x00,0x00,0x7b]
|
||||
vpsraw $123, 4096(%rdx), %ymm19
|
||||
|
||||
// CHECK: vpsraw $123, -4096(%rdx), %ymm19
|
||||
// CHECK: encoding: [0x62,0xf1,0x65,0x20,0x71,0x62,0x80,0x7b]
|
||||
vpsraw $123, -4096(%rdx), %ymm19
|
||||
|
||||
// CHECK: vpsraw $123, -4128(%rdx), %ymm19
|
||||
// CHECK: encoding: [0x62,0xf1,0x65,0x20,0x71,0xa2,0xe0,0xef,0xff,0xff,0x7b]
|
||||
vpsraw $123, -4128(%rdx), %ymm19
|
||||
|
||||
// CHECK: vpsrlvw %xmm19, %xmm22, %xmm30
|
||||
// CHECK: encoding: [0x62,0x22,0xcd,0x00,0x10,0xf3]
|
||||
vpsrlvw %xmm19, %xmm22, %xmm30
|
||||
|
||||
// CHECK: vpsrlvw %xmm19, %xmm22, %xmm30 {%k7}
|
||||
// CHECK: encoding: [0x62,0x22,0xcd,0x07,0x10,0xf3]
|
||||
vpsrlvw %xmm19, %xmm22, %xmm30 {%k7}
|
||||
|
||||
// CHECK: vpsrlvw %xmm19, %xmm22, %xmm30 {%k7} {z}
|
||||
// CHECK: encoding: [0x62,0x22,0xcd,0x87,0x10,0xf3]
|
||||
vpsrlvw %xmm19, %xmm22, %xmm30 {%k7} {z}
|
||||
|
||||
// CHECK: vpsrlvw (%rcx), %xmm22, %xmm30
|
||||
// CHECK: encoding: [0x62,0x62,0xcd,0x00,0x10,0x31]
|
||||
vpsrlvw (%rcx), %xmm22, %xmm30
|
||||
|
||||
// CHECK: vpsrlvw 291(%rax,%r14,8), %xmm22, %xmm30
|
||||
// CHECK: encoding: [0x62,0x22,0xcd,0x00,0x10,0xb4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vpsrlvw 291(%rax,%r14,8), %xmm22, %xmm30
|
||||
|
||||
// CHECK: vpsrlvw 2032(%rdx), %xmm22, %xmm30
|
||||
// CHECK: encoding: [0x62,0x62,0xcd,0x00,0x10,0x72,0x7f]
|
||||
vpsrlvw 2032(%rdx), %xmm22, %xmm30
|
||||
|
||||
// CHECK: vpsrlvw 2048(%rdx), %xmm22, %xmm30
|
||||
// CHECK: encoding: [0x62,0x62,0xcd,0x00,0x10,0xb2,0x00,0x08,0x00,0x00]
|
||||
vpsrlvw 2048(%rdx), %xmm22, %xmm30
|
||||
|
||||
// CHECK: vpsrlvw -2048(%rdx), %xmm22, %xmm30
|
||||
// CHECK: encoding: [0x62,0x62,0xcd,0x00,0x10,0x72,0x80]
|
||||
vpsrlvw -2048(%rdx), %xmm22, %xmm30
|
||||
|
||||
// CHECK: vpsrlvw -2064(%rdx), %xmm22, %xmm30
|
||||
// CHECK: encoding: [0x62,0x62,0xcd,0x00,0x10,0xb2,0xf0,0xf7,0xff,0xff]
|
||||
vpsrlvw -2064(%rdx), %xmm22, %xmm30
|
||||
|
||||
// CHECK: vpsrlvw %ymm27, %ymm25, %ymm30
|
||||
// CHECK: encoding: [0x62,0x02,0xb5,0x20,0x10,0xf3]
|
||||
vpsrlvw %ymm27, %ymm25, %ymm30
|
||||
|
||||
// CHECK: vpsrlvw %ymm27, %ymm25, %ymm30 {%k1}
|
||||
// CHECK: encoding: [0x62,0x02,0xb5,0x21,0x10,0xf3]
|
||||
vpsrlvw %ymm27, %ymm25, %ymm30 {%k1}
|
||||
|
||||
// CHECK: vpsrlvw %ymm27, %ymm25, %ymm30 {%k1} {z}
|
||||
// CHECK: encoding: [0x62,0x02,0xb5,0xa1,0x10,0xf3]
|
||||
vpsrlvw %ymm27, %ymm25, %ymm30 {%k1} {z}
|
||||
|
||||
// CHECK: vpsrlvw (%rcx), %ymm25, %ymm30
|
||||
// CHECK: encoding: [0x62,0x62,0xb5,0x20,0x10,0x31]
|
||||
vpsrlvw (%rcx), %ymm25, %ymm30
|
||||
|
||||
// CHECK: vpsrlvw 291(%rax,%r14,8), %ymm25, %ymm30
|
||||
// CHECK: encoding: [0x62,0x22,0xb5,0x20,0x10,0xb4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vpsrlvw 291(%rax,%r14,8), %ymm25, %ymm30
|
||||
|
||||
// CHECK: vpsrlvw 4064(%rdx), %ymm25, %ymm30
|
||||
// CHECK: encoding: [0x62,0x62,0xb5,0x20,0x10,0x72,0x7f]
|
||||
vpsrlvw 4064(%rdx), %ymm25, %ymm30
|
||||
|
||||
// CHECK: vpsrlvw 4096(%rdx), %ymm25, %ymm30
|
||||
// CHECK: encoding: [0x62,0x62,0xb5,0x20,0x10,0xb2,0x00,0x10,0x00,0x00]
|
||||
vpsrlvw 4096(%rdx), %ymm25, %ymm30
|
||||
|
||||
// CHECK: vpsrlvw -4096(%rdx), %ymm25, %ymm30
|
||||
// CHECK: encoding: [0x62,0x62,0xb5,0x20,0x10,0x72,0x80]
|
||||
vpsrlvw -4096(%rdx), %ymm25, %ymm30
|
||||
|
||||
// CHECK: vpsrlvw -4128(%rdx), %ymm25, %ymm30
|
||||
// CHECK: encoding: [0x62,0x62,0xb5,0x20,0x10,0xb2,0xe0,0xef,0xff,0xff]
|
||||
vpsrlvw -4128(%rdx), %ymm25, %ymm30
|
||||
|
||||
// CHECK: vpsravw %xmm27, %xmm28, %xmm28
|
||||
// CHECK: encoding: [0x62,0x02,0x9d,0x00,0x11,0xe3]
|
||||
vpsravw %xmm27, %xmm28, %xmm28
|
||||
|
||||
// CHECK: vpsravw %xmm27, %xmm28, %xmm28 {%k3}
|
||||
// CHECK: encoding: [0x62,0x02,0x9d,0x03,0x11,0xe3]
|
||||
vpsravw %xmm27, %xmm28, %xmm28 {%k3}
|
||||
|
||||
// CHECK: vpsravw %xmm27, %xmm28, %xmm28 {%k3} {z}
|
||||
// CHECK: encoding: [0x62,0x02,0x9d,0x83,0x11,0xe3]
|
||||
vpsravw %xmm27, %xmm28, %xmm28 {%k3} {z}
|
||||
|
||||
// CHECK: vpsravw (%rcx), %xmm28, %xmm28
|
||||
// CHECK: encoding: [0x62,0x62,0x9d,0x00,0x11,0x21]
|
||||
vpsravw (%rcx), %xmm28, %xmm28
|
||||
|
||||
// CHECK: vpsravw 291(%rax,%r14,8), %xmm28, %xmm28
|
||||
// CHECK: encoding: [0x62,0x22,0x9d,0x00,0x11,0xa4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vpsravw 291(%rax,%r14,8), %xmm28, %xmm28
|
||||
|
||||
// CHECK: vpsravw 2032(%rdx), %xmm28, %xmm28
|
||||
// CHECK: encoding: [0x62,0x62,0x9d,0x00,0x11,0x62,0x7f]
|
||||
vpsravw 2032(%rdx), %xmm28, %xmm28
|
||||
|
||||
// CHECK: vpsravw 2048(%rdx), %xmm28, %xmm28
|
||||
// CHECK: encoding: [0x62,0x62,0x9d,0x00,0x11,0xa2,0x00,0x08,0x00,0x00]
|
||||
vpsravw 2048(%rdx), %xmm28, %xmm28
|
||||
|
||||
// CHECK: vpsravw -2048(%rdx), %xmm28, %xmm28
|
||||
// CHECK: encoding: [0x62,0x62,0x9d,0x00,0x11,0x62,0x80]
|
||||
vpsravw -2048(%rdx), %xmm28, %xmm28
|
||||
|
||||
// CHECK: vpsravw -2064(%rdx), %xmm28, %xmm28
|
||||
// CHECK: encoding: [0x62,0x62,0x9d,0x00,0x11,0xa2,0xf0,0xf7,0xff,0xff]
|
||||
vpsravw -2064(%rdx), %xmm28, %xmm28
|
||||
|
||||
// CHECK: vpsravw %ymm17, %ymm28, %ymm20
|
||||
// CHECK: encoding: [0x62,0xa2,0x9d,0x20,0x11,0xe1]
|
||||
vpsravw %ymm17, %ymm28, %ymm20
|
||||
|
||||
// CHECK: vpsravw %ymm17, %ymm28, %ymm20 {%k5}
|
||||
// CHECK: encoding: [0x62,0xa2,0x9d,0x25,0x11,0xe1]
|
||||
vpsravw %ymm17, %ymm28, %ymm20 {%k5}
|
||||
|
||||
// CHECK: vpsravw %ymm17, %ymm28, %ymm20 {%k5} {z}
|
||||
// CHECK: encoding: [0x62,0xa2,0x9d,0xa5,0x11,0xe1]
|
||||
vpsravw %ymm17, %ymm28, %ymm20 {%k5} {z}
|
||||
|
||||
// CHECK: vpsravw (%rcx), %ymm28, %ymm20
|
||||
// CHECK: encoding: [0x62,0xe2,0x9d,0x20,0x11,0x21]
|
||||
vpsravw (%rcx), %ymm28, %ymm20
|
||||
|
||||
// CHECK: vpsravw 291(%rax,%r14,8), %ymm28, %ymm20
|
||||
// CHECK: encoding: [0x62,0xa2,0x9d,0x20,0x11,0xa4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vpsravw 291(%rax,%r14,8), %ymm28, %ymm20
|
||||
|
||||
// CHECK: vpsravw 4064(%rdx), %ymm28, %ymm20
|
||||
// CHECK: encoding: [0x62,0xe2,0x9d,0x20,0x11,0x62,0x7f]
|
||||
vpsravw 4064(%rdx), %ymm28, %ymm20
|
||||
|
||||
// CHECK: vpsravw 4096(%rdx), %ymm28, %ymm20
|
||||
// CHECK: encoding: [0x62,0xe2,0x9d,0x20,0x11,0xa2,0x00,0x10,0x00,0x00]
|
||||
vpsravw 4096(%rdx), %ymm28, %ymm20
|
||||
|
||||
// CHECK: vpsravw -4096(%rdx), %ymm28, %ymm20
|
||||
// CHECK: encoding: [0x62,0xe2,0x9d,0x20,0x11,0x62,0x80]
|
||||
vpsravw -4096(%rdx), %ymm28, %ymm20
|
||||
|
||||
// CHECK: vpsravw -4128(%rdx), %ymm28, %ymm20
|
||||
// CHECK: encoding: [0x62,0xe2,0x9d,0x20,0x11,0xa2,0xe0,0xef,0xff,0xff]
|
||||
vpsravw -4128(%rdx), %ymm28, %ymm20
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user