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Add memory operand version of conditional move.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12190 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alkis Evlogimenos
2004-03-07 03:19:11 +00:00
parent 5ae00066c6
commit 13d362f310
2 changed files with 10 additions and 3 deletions
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10
lib/Target/X86/X86InstrInfo.td
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@@ -294,9 +294,12 @@ let isTwoAddress = 1 in {
// Conditional moves. These are modelled as X = cmovXX Y, Z. Eventually // Conditional moves. These are modelled as X = cmovXX Y, Z. Eventually
// register allocated to cmovXX XY, Z // register allocated to cmovXX XY, Z
def CMOVE16rr : I<"cmove", 0x44, MRMSrcReg>, TB, OpSize; // if ==, R16 = R16 def CMOVE16rr : I <"cmove", 0x44, MRMSrcReg>, TB, OpSize; // if ==, R16 = R16
def CMOVNE32rr: I<"cmovne",0x45, MRMSrcReg>, TB; // if !=, R32 = R32 def CMOVE16rm : Im16<"cmove", 0x44, MRMSrcMem>, TB, OpSize; // if ==, R16 = [mem16]
def CMOVS32rr : I<"cmovs", 0x48, MRMSrcReg>, TB; // if signed, R32 = R32 def CMOVNE32rr: I <"cmovne",0x45, MRMSrcReg>, TB; // if !=, R32 = R32
def CMOVNE32rm: Im32<"cmovne",0x45, MRMSrcMem>, TB; // if !=, R32 = [mem32]
def CMOVS32rr : I <"cmovs", 0x48, MRMSrcReg>, TB; // if signed, R32 = R32
def CMOVS32rm : Im32<"cmovs", 0x48, MRMSrcMem>, TB; // if signed, R32 = [mem32]
// unary instructions // unary instructions
def NEG8r : I <"neg", 0xF6, MRM3r>; // R8 = -R8 = 0-R8 def NEG8r : I <"neg", 0xF6, MRM3r>; // R8 = -R8 = 0-R8
@@ -397,6 +400,7 @@ def XOR16mi8 : Im16i8<"xor", 0x83, MRM6m >, OpSize; // [mem16] ^= imm8
def XOR32mi8 : Im32i8<"xor", 0x83, MRM6m >; // [mem32] ^= imm8 def XOR32mi8 : Im32i8<"xor", 0x83, MRM6m >; // [mem32] ^= imm8
// Shift instructions // Shift instructions
// FIXME: provide shorter instructions when imm8 == 1
def SHL8rCL : I <"shl", 0xD2, MRM4r > , UsesCL; // R8 <<= cl def SHL8rCL : I <"shl", 0xD2, MRM4r > , UsesCL; // R8 <<= cl
def SHL16rCL : I <"shl", 0xD3, MRM4r >, OpSize, UsesCL; // R16 <<= cl def SHL16rCL : I <"shl", 0xD3, MRM4r >, OpSize, UsesCL; // R16 <<= cl
def SHL32rCL : I <"shl", 0xD3, MRM4r > , UsesCL; // R32 <<= cl def SHL32rCL : I <"shl", 0xD3, MRM4r > , UsesCL; // R32 <<= cl

3
lib/Target/X86/X86RegisterInfo.cpp
View File

@@ -260,6 +260,9 @@ bool X86RegisterInfo::foldMemoryOperand(MachineBasicBlock::iterator &MI,
case X86::MOV8rr: NI = MakeRMInst(X86::MOV8rm , FrameIndex, MI); break; case X86::MOV8rr: NI = MakeRMInst(X86::MOV8rm , FrameIndex, MI); break;
case X86::MOV16rr: NI = MakeRMInst(X86::MOV16rm, FrameIndex, MI); break; case X86::MOV16rr: NI = MakeRMInst(X86::MOV16rm, FrameIndex, MI); break;
case X86::MOV32rr: NI = MakeRMInst(X86::MOV32rm, FrameIndex, MI); break; case X86::MOV32rr: NI = MakeRMInst(X86::MOV32rm, FrameIndex, MI); break;
case X86::CMOVE16rr: NI = MakeRMInst(X86::CMOVE16rm , FrameIndex, MI); break;
case X86::CMOVNE32rr: NI = MakeRMInst(X86::CMOVNE32rm, FrameIndex, MI); break;
case X86::CMOVS32rr: NI = MakeRMInst(X86::CMOVS32rm , FrameIndex, MI); break;
case X86::ADD8rr: NI = MakeRMInst(X86::ADD8rm , FrameIndex, MI); break; case X86::ADD8rr: NI = MakeRMInst(X86::ADD8rm , FrameIndex, MI); break;
case X86::ADD16rr: NI = MakeRMInst(X86::ADD16rm, FrameIndex, MI); break; case X86::ADD16rr: NI = MakeRMInst(X86::ADD16rm, FrameIndex, MI); break;
case X86::ADD32rr: NI = MakeRMInst(X86::ADD32rm, FrameIndex, MI); break; case X86::ADD32rr: NI = MakeRMInst(X86::ADD32rm, FrameIndex, MI); break;