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STRH only needs the additional operand, not t2STRH. Also invert conditional
to match the one from the load emitter above. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119911 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -845,7 +845,6 @@ bool ARMFastISel::SelectLoad(const Instruction *I) {
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bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr) {
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unsigned StrOpc;
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bool isFloat = false;
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bool needReg0Op = false;
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switch (VT.getSimpleVT().SimpleTy) {
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default: return false;
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case MVT::i1: {
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@ -862,7 +861,6 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr) {
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break;
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case MVT::i16:
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StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH;
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needReg0Op = true;
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break;
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case MVT::i32:
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StrOpc = isThumb ? ARM::t2STRi12 : ARM::STRi12;
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@ -886,18 +884,16 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr) {
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if (isFloat)
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Addr.Offset /= 4;
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// FIXME: The 'needReg0Op' bit goes away once STRH is converted to
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// not use the mega-addrmode stuff.
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if (!needReg0Op)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(StrOpc))
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.addReg(SrcReg).addReg(Addr.Base.Reg).addImm(Addr.Offset));
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else
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// ARM::STRH needs an additional operand.
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if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(StrOpc))
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.addReg(SrcReg).addReg(Addr.Base.Reg)
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.addReg(0).addImm(Addr.Offset));
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else
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(StrOpc))
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.addReg(SrcReg).addReg(Addr.Base.Reg).addImm(Addr.Offset));
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return true;
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}
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