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Add a couple more instrs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24744 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -21,11 +21,13 @@ class F2 : InstV8 { // Format 2 instructions
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// Specific F2 classes: SparcV8 manual, page 44
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//
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class F2_1<bits<3> op2Val, string name> : F2 {
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class F2_1<bits<3> op2Val, dag ops, string asmstr> : F2 {
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bits<5> rd;
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dag OperandList = ops;
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let AsmString = asmstr;
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let op2 = op2Val;
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let Name = name;
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let Inst{29-25} = rd;
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}
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@ -149,12 +149,14 @@ def STDFQri : F3_2<3, 0b100110,
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"std $src, [$base+$offset]">;
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// Section B.9 - SETHI Instruction, p. 104
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def SETHIi: F2_1<0b100, "sethi">;
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def SETHIi: F2_1<0b100,
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(ops IntRegs:$dst, i32imm:$src),
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"sethi $src, $dst">;
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// Section B.10 - NOP Instruction, p. 105
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// (It's a special case of SETHI)
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let rd = 0, imm22 = 0 in
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def NOP : F2_1<0b100, "nop">;
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def NOP : F2_1<0b100, (ops), "nop">;
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// Section B.11 - Logical Instructions, p. 106
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def ANDrr : F3_1<2, 0b000001,
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@ -21,11 +21,13 @@ class F2 : InstV8 { // Format 2 instructions
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// Specific F2 classes: SparcV8 manual, page 44
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//
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class F2_1<bits<3> op2Val, string name> : F2 {
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class F2_1<bits<3> op2Val, dag ops, string asmstr> : F2 {
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bits<5> rd;
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dag OperandList = ops;
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let AsmString = asmstr;
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let op2 = op2Val;
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let Name = name;
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let Inst{29-25} = rd;
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}
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@ -149,12 +149,14 @@ def STDFQri : F3_2<3, 0b100110,
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"std $src, [$base+$offset]">;
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// Section B.9 - SETHI Instruction, p. 104
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def SETHIi: F2_1<0b100, "sethi">;
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def SETHIi: F2_1<0b100,
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(ops IntRegs:$dst, i32imm:$src),
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"sethi $src, $dst">;
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// Section B.10 - NOP Instruction, p. 105
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// (It's a special case of SETHI)
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let rd = 0, imm22 = 0 in
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def NOP : F2_1<0b100, "nop">;
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def NOP : F2_1<0b100, (ops), "nop">;
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// Section B.11 - Logical Instructions, p. 106
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def ANDrr : F3_1<2, 0b000001,
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