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Propagate debug loc info in ADDC and ADDE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63367 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1135,22 +1135,25 @@ SDValue DAGCombiner::visitADDC(SDNode *N) {
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// If the flag result is dead, turn this into an ADD.
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if (N->hasNUsesOfValue(0, 1))
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return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
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DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
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return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
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DAG.getNode(ISD::CARRY_FALSE,
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N->getDebugLoc(), MVT::Flag));
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// canonicalize constant to RHS.
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if (N0C && !N1C)
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return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0);
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return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
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// fold (addc x, 0) -> x + no carry out
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if (N1C && N1C->isNullValue())
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return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
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return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
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N->getDebugLoc(), MVT::Flag));
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// fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
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APInt LHSZero, LHSOne;
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APInt RHSZero, RHSOne;
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APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
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DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
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if (LHSZero.getBoolValue()) {
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DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
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@ -1158,8 +1161,9 @@ SDValue DAGCombiner::visitADDC(SDNode *N) {
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// If all possibly-set bits on the RHS are clear on the LHS, return an OR.
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if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
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(LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
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return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
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DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
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return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
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DAG.getNode(ISD::CARRY_FALSE,
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N->getDebugLoc(), MVT::Flag));
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}
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return SDValue();
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@ -1171,21 +1175,19 @@ SDValue DAGCombiner::visitADDE(SDNode *N) {
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SDValue CarryIn = N->getOperand(2);
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ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
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//MVT VT = N0.getValueType();
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// canonicalize constant to RHS
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if (N0C && !N1C)
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return DAG.getNode(ISD::ADDE, N->getVTList(), N1, N0, CarryIn);
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return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
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N1, N0, CarryIn);
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// fold (adde x, y, false) -> (addc x, y)
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if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
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return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0);
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return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
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return SDValue();
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}
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SDValue DAGCombiner::visitSUB(SDNode *N) {
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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