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https://github.com/c64scene-ar/llvm-6502.git
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Scavenge a register using the register scavenger when needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34966 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -85,11 +85,6 @@ ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
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: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
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TII(tii), STI(sti),
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FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) {
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RS = (EnableScavenging) ? new RegScavenger() : NULL;
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}
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ARMRegisterInfo::~ARMRegisterInfo() {
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delete RS;
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}
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bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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@ -328,6 +323,25 @@ BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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return Reserved;
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}
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bool
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ARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
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switch (Reg) {
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default: break;
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case ARM::SP:
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case ARM::PC:
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return true;
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case ARM::R7:
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case ARM::R11:
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if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
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return true;
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break;
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case ARM::R9:
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return STI.isR9Reserved();
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}
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return false;
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}
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bool
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ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
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const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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@ -918,15 +932,34 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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// to form it with a series of ADDri's. Do this by taking 8-bit chunks
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// out of 'Offset'.
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unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
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assert(ScratchReg && "Unable to find a free register!");
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if (ScratchReg == 0)
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// No register is "free". Scavenge a register.
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ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II);
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emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
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isSub ? -Offset : Offset, TII);
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MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
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}
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}
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void ARMRegisterInfo::
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processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const {
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static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
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const MachineFrameInfo *FFI = MF.getFrameInfo();
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int Offset = 0;
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for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
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int FixedOff = -FFI->getObjectOffset(i);
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if (FixedOff > Offset) Offset = FixedOff;
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}
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for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
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Offset += FFI->getObjectSize(i);
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unsigned Align = FFI->getObjectAlignment(i);
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// Adjust to alignment boundary
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Offset = (Offset+Align-1)/Align*Align;
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}
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return (unsigned)Offset;
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}
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void
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ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS) const {
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// This tells PEI to spill the FP as if it is any other callee-save register
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// to take advantage the eliminateFrameIndex machinery. This also ensures it
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// is spilled in the order specified by getCalleeSavedRegs() to make it easier
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@ -1020,6 +1053,7 @@ processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const {
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}
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}
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bool ExtraCSSpill = false;
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if (!CanEliminateFrame || hasFP(MF)) {
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AFI->setHasStackFrame(true);
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@ -1032,6 +1066,7 @@ processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const {
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UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
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UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
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ForceLRSpill = false;
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ExtraCSSpill = true;
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}
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// Darwin ABI requires FP to point to the stack slot that contains the
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@ -1050,10 +1085,74 @@ processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const {
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unsigned Reg = UnspilledCS1GPRs.front();
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MF.changePhyRegUsed(Reg, true);
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AFI->setCSRegisterIsSpilled(Reg);
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if (!isReservedReg(MF, Reg))
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ExtraCSSpill = true;
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} else if (!UnspilledCS2GPRs.empty()) {
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unsigned Reg = UnspilledCS2GPRs.front();
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MF.changePhyRegUsed(Reg, true);
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AFI->setCSRegisterIsSpilled(Reg);
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if (!isReservedReg(MF, Reg))
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ExtraCSSpill = true;
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}
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}
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// Estimate if we might need to scavenge a register at some point in order
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// to materialize a stack offset. If so, either spill one additiona
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// callee-saved register or reserve a special spill slot to facilitate
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// register scavenging.
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if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) {
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MachineFrameInfo *MFI = MF.getFrameInfo();
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unsigned Size = estimateStackSize(MF, MFI);
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unsigned Limit = (1 << 12) - 1;
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for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
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for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
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for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
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if (I->getOperand(i).isFrameIndex()) {
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unsigned Opcode = I->getOpcode();
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const TargetInstrDescriptor &Desc = TII.get(Opcode);
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unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
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if (AddrMode == ARMII::AddrMode3) {
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Limit = (1 << 8) - 1;
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goto DoneEstimating;
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} else if (AddrMode == ARMII::AddrMode5) {
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Limit = ((1 << 8) - 1) * 4;
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goto DoneEstimating;
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}
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}
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}
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DoneEstimating:
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if (Size >= Limit) {
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// If any non-reserved CS register isn't spilled, just spill one or two
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// extra. That should take care of it!
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unsigned NumExtras = TargetAlign / 4;
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SmallVector<unsigned, 2> Extras;
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while (NumExtras && !UnspilledCS1GPRs.empty()) {
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unsigned Reg = UnspilledCS1GPRs.back();
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UnspilledCS1GPRs.pop_back();
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if (!isReservedReg(MF, Reg)) {
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Extras.push_back(Reg);
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NumExtras--;
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}
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}
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while (NumExtras && !UnspilledCS2GPRs.empty()) {
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unsigned Reg = UnspilledCS2GPRs.back();
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UnspilledCS2GPRs.pop_back();
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if (!isReservedReg(MF, Reg)) {
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Extras.push_back(Reg);
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NumExtras--;
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}
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}
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if (Extras.size() && NumExtras == 0) {
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for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
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MF.changePhyRegUsed(Extras[i], true);
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AFI->setCSRegisterIsSpilled(Extras[i]);
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}
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} else {
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// Reserve a slot closest to SP or frame pointer.
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const TargetRegisterClass *RC = &ARM::GPRRegClass;
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RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
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RC->getAlignment()));
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}
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}
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}
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}
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@ -27,17 +27,12 @@ struct ARMRegisterInfo : public ARMGenRegisterInfo {
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const TargetInstrInfo &TII;
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const ARMSubtarget &STI;
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private:
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/// RS - An instance of the register scavenger.
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RegScavenger *RS;
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/// FramePtr - ARM physical register used as frame ptr.
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unsigned FramePtr;
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public:
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ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
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~ARMRegisterInfo();
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// ARM::LR, return the number that it corresponds to (e.g. 14).
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static unsigned getRegisterNumbering(unsigned RegEnum);
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@ -74,6 +69,8 @@ public:
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BitVector getReservedRegs(const MachineFunction &MF) const;
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bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
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bool requiresRegisterScavenging(const MachineFunction &MF) const;
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bool hasFP(const MachineFunction &MF) const;
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@ -85,7 +82,8 @@ public:
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void eliminateFrameIndex(MachineBasicBlock::iterator II,
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RegScavenger *RS = NULL) const;
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void processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const;
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void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS = NULL) const;
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void emitPrologue(MachineFunction &MF) const;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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