From 141ec63962b6fca66ab0007ffc6e50de46a22b6f Mon Sep 17 00:00:00 2001
From: Cameron Zwarich <zwarich@apple.com>
Date: Wed, 18 May 2011 02:29:50 +0000
Subject: [PATCH] Fix typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131519 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMISelLowering.cpp | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index e3bc3fa9b3d..18d30083f8f 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -4866,13 +4866,13 @@ ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
 
   MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
   unsigned scratch =
-    MRI.createVirtualRegister(isThumb2 ? ARM::tGPRRegisterClass
+    MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass
                                        : ARM::GPRRegisterClass);
 
   if (isThumb2) {
-    MRI.constrainRegClass(dest, ARM::tGPRRegisterClass);
-    MRI.constrainRegClass(oldval, ARM::tGPRRegisterClass);
-    MRI.constrainRegClass(newval, ARM::tGPRRegisterClass);
+    MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
+    MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass);
+    MRI.constrainRegClass(newval, ARM::rGPRRegisterClass);
   }
 
   unsigned ldrOpc, strOpc;