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add one addressing mode description hook to rule them all.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35520 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-03-30 23:14:50 +00:00
parent 00ef8d45e2
commit 1436bb657d
2 changed files with 55 additions and 1 deletions
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22
include/llvm/Target/TargetLowering.h
View File

@ -853,9 +853,29 @@ public:
MachineBasicBlock *MBB);
//===--------------------------------------------------------------------===//
// Loop Strength Reduction hooks
// Addressing mode description hooks (used by LSR etc).
//
/// AddrMode - This represents an addressing mode of:
/// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
/// If BaseGV is null, there is no BaseGV.
/// If BaseOffs is zero, there is no base offset.
/// If HasBaseReg is false, there is no base register.
/// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
/// no scale.
///
struct AddrMode {
GlobalValue *BaseGV;
int64_t BaseOffs;
bool HasBaseReg;
int64_t Scale;
};
/// isLegalAddressingMode - Return true if the addressing mode represented by
/// AM is legal for this target, for a load/store of the specified type.
/// TODO: Handle pre/postinc as well.
virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
/// isLegalAddressImmediate - Return true if the integer value can be used as
/// the offset of the target addressing mode for load / store of the given
/// type.

34
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -1940,6 +1940,40 @@ getRegForInlineAsmConstraint(const std::string &Constraint,
// Loop Strength Reduction hooks
//===----------------------------------------------------------------------===//
/// isLegalAddressingMode - Return true if the addressing mode represented
/// by AM is legal for this target, for a load/store of the specified type.
bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
const Type *Ty) const {
// The default implementation of this implements a conservative RISCy, r+r and
// r+i addr mode.
// Allows a sign-extended 16-bit immediate field.
if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
return false;
// No global is ever allowed as a base.
if (AM.BaseGV)
return false;
// Only support r+r,
switch (AM.Scale) {
case 0: // "r+i" or just "i", depending on HasBaseReg.
break;
case 1:
if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
return false;
// Otherwise we have r+r or r+i.
break;
case 2:
if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
return false;
// Allow 2*r as r+r.
break;
}
return true;
}
/// isLegalAddressImmediate - Return true if the integer value can be used as
/// the offset of the target addressing mode for load / store of the given
/// type.