From 144d8f09e139f691cafadbc17873943ba4c465f3 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Thu, 9 Nov 2006 17:55:04 +0000 Subject: [PATCH] Rename ISD::MemOpAddrMode to ISD::MemIndexedMode git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31595 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SelectionDAG.h | 4 ++-- include/llvm/CodeGen/SelectionDAGNodes.h | 23 ++++++++++++----------- include/llvm/Target/TargetLowering.h | 6 +++--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 ++-- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 16 +++++++++------- lib/Target/PowerPC/PPCISelLowering.cpp | 2 +- lib/Target/PowerPC/PPCISelLowering.h | 2 +- 7 files changed, 30 insertions(+), 27 deletions(-) diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index 2448a65ee6a..2622098416b 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -316,7 +316,7 @@ public: SDOperand Chain, SDOperand Ptr, const Value *SV, int SVOffset, MVT::ValueType EVT, bool isVolatile=false); SDOperand getIndexedLoad(SDOperand OrigLoad, SDOperand Base, - SDOperand Offset, ISD::MemOpAddrMode AM); + SDOperand Offset, ISD::MemIndexedMode AM); SDOperand getVecLoad(unsigned Count, MVT::ValueType VT, SDOperand Chain, SDOperand Ptr, SDOperand SV); @@ -328,7 +328,7 @@ public: const Value *SV, int SVOffset, MVT::ValueType TVT, bool isVolatile=false); SDOperand getIndexedStore(SDOperand OrigStoe, SDOperand Base, - SDOperand Offset, ISD::MemOpAddrMode AM); + SDOperand Offset, ISD::MemIndexedMode AM); // getSrcValue - construct a node to track a Value* through the backend SDOperand getSrcValue(const Value* I, int offset = 0); diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index 1ed4dc43c56..ef27bc19bd2 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -524,8 +524,8 @@ namespace ISD { bool isBuildVectorAllZeros(const SDNode *N); //===--------------------------------------------------------------------===// - /// MemOpAddrMode enum - This enum defines the three load / store addressing - /// modes. + /// MemIndexedMode enum - This enum defines the load / store indexed + /// addressing modes. /// /// UNINDEXED "Normal" load / store. The effective address is already /// computed and is available in the base pointer. The offset @@ -552,12 +552,13 @@ namespace ISD { /// computation); a post-indexed store produces one value (the /// the result of the base +/- offset computation). /// - enum MemOpAddrMode { + enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, - POST_DEC + POST_DEC, + LAST_INDEXED_MODE }; //===--------------------------------------------------------------------===// @@ -865,7 +866,7 @@ public: /// getOperationName - Return the opcode of this operation for printing. /// const char* getOperationName(const SelectionDAG *G = 0) const; - static const char* getAddressingModeName(ISD::MemOpAddrMode AM); + static const char* getIndexedModeName(ISD::MemIndexedMode AM); void dump() const; void dump(const SelectionDAG *G) const; @@ -1383,7 +1384,7 @@ public: /// class LoadSDNode : public SDNode { // AddrMode - unindexed, pre-indexed, post-indexed. - ISD::MemOpAddrMode AddrMode; + ISD::MemIndexedMode AddrMode; // ExtType - non-ext, anyext, sext, zext. ISD::LoadExtType ExtType; @@ -1405,7 +1406,7 @@ class LoadSDNode : public SDNode { protected: friend class SelectionDAG; LoadSDNode(SDOperand Chain, SDOperand Ptr, SDOperand Off, - ISD::MemOpAddrMode AM, ISD::LoadExtType ETy, MVT::ValueType LVT, + ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT::ValueType LVT, const Value *SV, int O=0, unsigned Align=1, bool Vol=false) : SDNode(ISD::LOAD, Chain, Ptr, Off), AddrMode(AM), ExtType(ETy), LoadedVT(LVT), SrcValue(SV), SVOffset(O), @@ -1418,7 +1419,7 @@ public: const SDOperand getChain() const { return getOperand(0); } const SDOperand getBasePtr() const { return getOperand(1); } const SDOperand getOffset() const { return getOperand(2); } - ISD::MemOpAddrMode getAddressingMode() const { return AddrMode; } + ISD::MemIndexedMode getAddressingMode() const { return AddrMode; } ISD::LoadExtType getExtensionType() const { return ExtType; } MVT::ValueType getLoadedVT() const { return LoadedVT; } const Value *getSrcValue() const { return SrcValue; } @@ -1436,7 +1437,7 @@ public: /// class StoreSDNode : public SDNode { // AddrMode - unindexed, pre-indexed, post-indexed. - ISD::MemOpAddrMode AddrMode; + ISD::MemIndexedMode AddrMode; // IsTruncStore - True is the op does a truncation before store. bool IsTruncStore; @@ -1458,7 +1459,7 @@ class StoreSDNode : public SDNode { protected: friend class SelectionDAG; StoreSDNode(SDOperand Chain, SDOperand Value, SDOperand Ptr, SDOperand Off, - ISD::MemOpAddrMode AM, bool isTrunc, MVT::ValueType SVT, + ISD::MemIndexedMode AM, bool isTrunc, MVT::ValueType SVT, const Value *SV, int O=0, unsigned Align=0, bool Vol=false) : SDNode(ISD::STORE, Chain, Value, Ptr, Off), AddrMode(AM), IsTruncStore(isTrunc), StoredVT(SVT), SrcValue(SV), @@ -1472,7 +1473,7 @@ public: const SDOperand getValue() const { return getOperand(1); } const SDOperand getBasePtr() const { return getOperand(2); } const SDOperand getOffset() const { return getOperand(3); } - ISD::MemOpAddrMode getAddressingMode() const { return AddrMode; } + ISD::MemIndexedMode getAddressingMode() const { return AddrMode; } bool isTruncatingStore() const { return IsTruncStore; } MVT::ValueType getStoredVT() const { return StoredVT; } const Value *getSrcValue() const { return SrcValue; } diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index d775d8278f2..5a4a5b6b301 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -377,7 +377,7 @@ public: /// can be legally represented as pre-indexed load / store address. virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base, SDOperand &Offset, - ISD::MemOpAddrMode &AM, + ISD::MemIndexedMode &AM, SelectionDAG &DAG) { return false; } @@ -387,7 +387,7 @@ public: /// combined with a load / store to form a post-indexed load / store. virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDOperand &Base, SDOperand &Offset, - ISD::MemOpAddrMode &AM, + ISD::MemIndexedMode &AM, SelectionDAG &DAG) { return false; } @@ -869,7 +869,7 @@ private: /// LegalizeAction that indicates how instruction selection should deal with /// the store. uint64_t StoreXActions; - + ValueTypeActionImpl ValueTypeActions; std::vector LegalFPImmediates; diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index d211077b90d..8bbcd2651ca 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -202,7 +202,7 @@ namespace { Ptr.Val->use_size() > 1) { SDOperand BasePtr; SDOperand Offset; - ISD::MemOpAddrMode AM = ISD::UNINDEXED; + ISD::MemIndexedMode AM = ISD::UNINDEXED; if (TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) { // Try turning it into a pre-indexed load / store except when // 1) Another use of base ptr is a predecessor of N. If ptr is folded @@ -298,7 +298,7 @@ namespace { SDOperand BasePtr; SDOperand Offset; - ISD::MemOpAddrMode AM = ISD::UNINDEXED; + ISD::MemIndexedMode AM = ISD::UNINDEXED; if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM,DAG)) { if (Ptr == Offset) std::swap(BasePtr, Offset); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index f2e9ea8c83c..3b51679810e 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1619,8 +1619,9 @@ SDOperand SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT::ValueType VT, return SDOperand(N, 0); } -SDOperand SelectionDAG::getIndexedLoad(SDOperand OrigLoad, SDOperand Base, - SDOperand Offset, ISD::MemOpAddrMode AM){ +SDOperand +SelectionDAG::getIndexedLoad(SDOperand OrigLoad, SDOperand Base, + SDOperand Offset, ISD::MemIndexedMode AM) { LoadSDNode *LD = cast(OrigLoad); assert(LD->getOffset().getOpcode() == ISD::UNDEF && "Load is already a indexed load!"); @@ -1722,8 +1723,9 @@ SDOperand SelectionDAG::getTruncStore(SDOperand Chain, SDOperand Val, return SDOperand(N, 0); } -SDOperand SelectionDAG::getIndexedStore(SDOperand OrigStore, SDOperand Base, - SDOperand Offset, ISD::MemOpAddrMode AM){ +SDOperand +SelectionDAG::getIndexedStore(SDOperand OrigStore, SDOperand Base, + SDOperand Offset, ISD::MemIndexedMode AM) { StoreSDNode *ST = cast(OrigStore); assert(ST->getOffset().getOpcode() == ISD::UNDEF && "Store is already a indexed store!"); @@ -2841,7 +2843,7 @@ const char *SDNode::getOperationName(const SelectionDAG *G) const { } } -const char *SDNode::getAddressingModeName(ISD::MemOpAddrMode AM) { +const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { switch (AM) { default: return ""; @@ -2943,7 +2945,7 @@ void SDNode::dump(const SelectionDAG *G) const { if (doExt) std::cerr << MVT::getValueTypeString(LD->getLoadedVT()) << ">"; - const char *AM = getAddressingModeName(LD->getAddressingMode()); + const char *AM = getIndexedModeName(LD->getAddressingMode()); if (AM != "") std::cerr << " " << AM; } else if (const StoreSDNode *ST = dyn_cast(this)) { @@ -2951,7 +2953,7 @@ void SDNode::dump(const SelectionDAG *G) const { std::cerr << " getStoredVT()) << ">"; - const char *AM = getAddressingModeName(ST->getAddressingMode()); + const char *AM = getIndexedModeName(ST->getAddressingMode()); if (AM != "") std::cerr << " " << AM; } diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index bd04a806253..a850e473ddd 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -853,7 +853,7 @@ bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, /// can be legally represented as pre-indexed load / store address. bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, SDOperand &Offset, - ISD::MemOpAddrMode &AM, + ISD::MemIndexedMode &AM, SelectionDAG &DAG) { return false; diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h index 87b938a0759..cb4dc473f13 100644 --- a/lib/Target/PowerPC/PPCISelLowering.h +++ b/lib/Target/PowerPC/PPCISelLowering.h @@ -182,7 +182,7 @@ namespace llvm { /// can be legally represented as pre-indexed load / store address. virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base, SDOperand &Offset, - ISD::MemOpAddrMode &AM, + ISD::MemIndexedMode &AM, SelectionDAG &DAG); /// SelectAddressRegReg - Given the specified addressed, check to see if it