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Add BCTR and LWZU instruction opcodes

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17851 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-11-15 21:20:09 +00:00
parent 748d82e730
commit 145a5a3746
1 changed files with 7 additions and 2 deletions
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9
lib/Target/PowerPC/PPCInstrInfo.td
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@ -14,8 +14,11 @@
include "PowerPCInstrFormats.td"
let isTerminator = 1, isReturn = 1 in
def BLR : XLForm_2_ext<19, 16, 20, 31, 1, 0, 0, (ops), "blr">;
let isTerminator = 1 in {
let isReturn = 1 in
def BLR : XLForm_2_ext<19, 16, 20, 31, 1, 0, 0, (ops), "blr">;
def BCTR : XLForm_2_ext<19, 528, 20, 31, 1, 0, 0, (ops), "bctr">;
}
def u5imm : Operand<i8> {
let PrintMethod = "printU5ImmOperand";
@ -98,6 +101,8 @@ def LMW : DForm_1<46, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
"lmw $rD, $disp($rA)">;
def LWZ : DForm_1<32, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
"lwz $rD, $disp($rA)">;
def LWZU : DForm_1<33, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
"lwzu $rD, $disp($rA)">;
}
def ADDI : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
"addi $rD, $rA, $imm">;