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Instead of emitting an implicit use for the super-register of

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X86::CL that was used, emit an EXTRACT_SUBREG from the CL
super-register to CL. This more precisely describes how the
CL register is being used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57264 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-10-07 21:50:36 +00:00
parent 76e9661b6c
commit 145b828014
1 changed files with 10 additions and 6 deletions
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16
lib/Target/X86/X86FastISel.cpp
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@ -866,12 +866,16 @@ bool X86FastISel::X86SelectShift(Instruction *I) {
unsigned Op1Reg = getRegForValue(I->getOperand(1));
if (Op1Reg == 0) return false;
TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
// The shift instruction uses X86::CL. If we defined a super-register
// of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
// we're doing here.
if (CReg != X86::CL)
BuildMI(MBB, TII.get(TargetInstrInfo::EXTRACT_SUBREG), X86::CL)
.addReg(CReg).addImm(X86::SUBREG_8BIT);
unsigned ResultReg = createResultReg(RC);
BuildMI(MBB, TII.get(OpReg), ResultReg).addReg(Op0Reg)
// FIXME: The "Local" register allocator's physreg liveness doesn't
// recognize subregs. Adding the superreg of CL that's actually defined
// prevents it from being re-allocated for this instruction.
.addReg(CReg, false, true);
BuildMI(MBB, TII.get(OpReg), ResultReg).addReg(Op0Reg);
UpdateValueMap(I, ResultReg);
return true;
}
@ -976,7 +980,7 @@ bool X86FastISel::X86SelectTrunc(Instruction *I) {
BuildMI(MBB, TII.get(CopyOpc), CopyReg).addReg(InputReg);
// Then issue an extract_subreg.
unsigned ResultReg = FastEmitInst_extractsubreg(CopyReg,1); // x86_subreg_8bit
unsigned ResultReg = FastEmitInst_extractsubreg(CopyReg, X86::SUBREG_8BIT);
if (!ResultReg)
return false;