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ARM STRD assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137342 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -680,35 +680,6 @@ class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
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let Inst{24} = 1; // P bit
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let Inst{27-25} = 0b000;
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}
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class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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: I<oops, iops, AddrMode3, 4, IndexModePre, f, itin,
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opc, asm, cstr, pattern> {
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let Inst{4} = 1;
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let Inst{5} = 1; // H bit
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let Inst{6} = 1; // S bit
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let Inst{7} = 1;
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let Inst{20} = 0; // L bit
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let Inst{21} = 1; // W bit
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let Inst{24} = 1; // P bit
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let Inst{27-25} = 0b000;
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}
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// Post-indexed stores
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class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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: I<oops, iops, AddrMode3, 4, IndexModePost, f, itin,
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opc, asm, cstr, pattern> {
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let Inst{4} = 1;
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let Inst{5} = 1; // H bit
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let Inst{6} = 1; // S bit
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let Inst{7} = 1;
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let Inst{20} = 0; // L bit
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let Inst{21} = 0; // W bit
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let Inst{24} = 0; // P bit
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let Inst{27-25} = 0b000;
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}
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// addrmode4 instructions
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class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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@ -2369,42 +2369,35 @@ def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
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[(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
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GPR:$Rn, am3offset:$offset))]>;
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// For disassembly only
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
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def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
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(ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
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StMiscFrm, IIC_iStore_d_ru,
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"strd", "\t$src1, $src2, [$base, $offset]!",
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"$base = $base_wb", []> {
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bits<4> src1;
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bits<4> base;
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bits<10> offset;
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let Inst{23} = offset{8}; // U bit
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let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
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let Inst{19-16} = base;
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let Inst{15-12} = src1;
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let Inst{11-8} = offset{7-4};
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let Inst{3-0} = offset{3-0};
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def STRD_PRE : AI3ldstidx<0b1111, 0, 1, 1, (outs GPR:$Rn_wb),
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(ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
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IndexModePre, StMiscFrm, IIC_iStore_d_ru,
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"strd", "\t$Rt, $Rt2, $addr!",
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"$addr.base = $Rn_wb", []> {
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bits<14> addr;
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let Inst{23} = addr{8}; // U bit
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let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
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let Inst{19-16} = addr{12-9}; // Rn
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let Inst{11-8} = addr{7-4}; // imm7_4/zero
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let Inst{3-0} = addr{3-0}; // imm3_0/Rm
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let DecoderMethod = "DecodeAddrMode3Instruction";
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let AsmMatchConverter = "cvtStrdPre";
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}
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// For disassembly only
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def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
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(ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
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StMiscFrm, IIC_iStore_d_ru,
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"strd", "\t$src1, $src2, [$base], $offset",
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"$base = $base_wb", []> {
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bits<4> src1;
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bits<4> base;
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def STRD_POST: AI3ldstidx<0b1111, 0, 1, 0, (outs GPR:$Rn_wb),
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(ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
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am3offset:$offset),
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IndexModePost, StMiscFrm, IIC_iStore_d_ru,
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"strd", "\t$Rt, $Rt2, $addr, $offset",
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"$addr.base = $Rn_wb", []> {
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bits<10> offset;
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let Inst{23} = offset{8}; // U bit
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let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
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let Inst{19-16} = base;
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let Inst{15-12} = src1;
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let Inst{11-8} = offset{7-4};
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let Inst{3-0} = offset{3-0};
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bits<4> addr;
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let Inst{23} = offset{8}; // U bit
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let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
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let Inst{19-16} = addr;
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let Inst{11-8} = offset{7-4}; // imm7_4/zero
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let Inst{3-0} = offset{3-0}; // imm3_0/Rm
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let DecoderMethod = "DecodeAddrMode3Instruction";
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}
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} // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
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@ -133,6 +133,8 @@ class ARMAsmParser : public MCTargetAsmParser {
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const SmallVectorImpl<MCParsedAsmOperand*> &);
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bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &);
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bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &);
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bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &);
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@ -2224,6 +2226,24 @@ cvtLdrdPre(MCInst &Inst, unsigned Opcode,
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return true;
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}
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/// cvtStrdPre - Convert parsed operands to MCInst.
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/// Needed here because the Asm Gen Matcher can't handle properly tied operands
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/// when they refer multiple MIOperands inside a single one.
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bool ARMAsmParser::
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cvtStrdPre(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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// Create a writeback register dummy placeholder.
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Inst.addOperand(MCOperand::CreateImm(0));
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// Rt, Rt2
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((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
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((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
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// addr
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((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
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// pred
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((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
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return true;
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}
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/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
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/// Needed here because the Asm Gen Matcher can't handle properly tied operands
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/// when they refer multiple MIOperands inside a single one.
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@ -2850,7 +2870,15 @@ validateInstruction(MCInst &Inst,
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"destination operands must be sequential");
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return false;
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}
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case ARM::STRD:
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case ARM::STRD: {
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// Rt2 must be Rt + 1.
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unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
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unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
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if (Rt2 != Rt + 1)
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return Error(Operands[3]->getStartLoc(),
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"source operands must be sequential");
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return false;
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}
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case ARM::STRD_PRE:
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case ARM::STRD_POST:
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case ARM::STREXD: {
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@ -2858,7 +2886,7 @@ validateInstruction(MCInst &Inst,
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unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
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unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
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if (Rt2 != Rt + 1)
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return Error(Operands[4]->getStartLoc(),
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return Error(Operands[3]->getStartLoc(),
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"source operands must be sequential");
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return false;
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}
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@ -389,3 +389,42 @@ _func:
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@ CHECK: strbt r5, [r6], #-13 @ encoding: [0x0d,0x50,0x66,0xe4]
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@ CHECK: strbt r4, [r9], r5 @ encoding: [0x05,0x40,0xe9,0xe6]
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@ CHECK: strbt r3, [r8], -r2, lsl #3 @ encoding: [0x82,0x31,0x68,0xe6]
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@------------------------------------------------------------------------------
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@ STRD (immediate)
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@------------------------------------------------------------------------------
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strd r1, r2, [r4]
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strd r2, r3, [r6, #1]
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strd r3, r4, [r7, #22]!
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strd r4, r5, [r8], #7
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strd r5, r6, [sp], #0
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strd r6, r7, [lr], #+0
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strd r7, r8, [r9], #-0
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@ CHECK: strd r1, r2, [r4] @ encoding: [0xf0,0x10,0xc4,0xe1]
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@ CHECK: strd r2, r3, [r6, #1] @ encoding: [0xf1,0x20,0xc6,0xe1]
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@ CHECK: strd r3, r4, [r7, #22]! @ encoding: [0xf6,0x31,0xe7,0xe1]
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@ CHECK: strd r4, r5, [r8], #7 @ encoding: [0xf7,0x40,0xc8,0xe0]
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@ CHECK: strd r5, r6, [sp], #0 @ encoding: [0xf0,0x50,0xcd,0xe0]
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@ CHECK: strd r6, r7, [lr], #0 @ encoding: [0xf0,0x60,0xce,0xe0]
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@ CHECK: strd r7, r8, [r9], #-0 @ encoding: [0xf0,0x70,0x49,0xe0]
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@------------------------------------------------------------------------------
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@ FIXME: STRD (label)
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@------------------------------------------------------------------------------
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@------------------------------------------------------------------------------
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@ STRD (register)
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@------------------------------------------------------------------------------
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strd r8, r9, [r4, r1]
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strd r7, r8, [r3, r9]!
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strd r6, r7, [r5], r8
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strd r5, r6, [r12], -r10
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@ CHECK: strd r8, r9, [r4, r1] @ encoding: [0xf1,0x80,0x84,0xe1]
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@ CHECK: strd r7, r8, [r3, r9]! @ encoding: [0xf9,0x70,0xa3,0xe1]
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@ CHECK: strd r6, r7, [r5], r8 @ encoding: [0xf8,0x60,0x85,0xe0]
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@ CHECK: strd r5, r6, [r12], -r10 @ encoding: [0xfa,0x50,0x0c,0xe0]
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