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https://github.com/c64scene-ar/llvm-6502.git
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Code generation for 'fence' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136283 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -592,6 +592,11 @@ namespace ISD {
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// and produces an output chain.
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MEMBARRIER,
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// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope)
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// This corresponds to the fence instruction. It takes an input chain, and
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// two integer constants: an AtomicOrdering and a SynchronizationScope.
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ATOMIC_FENCE,
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// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
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// this corresponds to the atomic.lcs intrinsic.
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// cmp is compared to *ptr, and if equal, swap is stored in *ptr.
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@ -205,6 +205,9 @@ def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barier
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SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
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SDTCisInt<0>
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]>;
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def SDTAtomicFence : SDTypeProfile<0, 2, [
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SDTCisSameAs<0,1>, SDTCisPtrTy<0>
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]>;
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def SDTAtomic3 : SDTypeProfile<1, 3, [
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SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
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]>;
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@ -397,6 +400,9 @@ def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch,
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def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier,
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[SDNPHasChain, SDNPSideEffect]>;
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def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence,
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[SDNPHasChain, SDNPSideEffect]>;
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def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3,
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
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def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2,
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@ -2955,8 +2955,10 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Results.push_back(DAG.getConstant(0, MVT::i32));
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Results.push_back(Node->getOperand(0));
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break;
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case ISD::ATOMIC_FENCE:
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case ISD::MEMBARRIER: {
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// If the target didn't lower this, lower it to '__sync_synchronize()' call
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// FIXME: handle "fence singlethread" more efficiently.
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TargetLowering::ArgListTy Args;
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std::pair<SDValue, SDValue> CallResult =
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TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
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@ -5769,6 +5769,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
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#endif
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case ISD::PREFETCH: return "Prefetch";
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case ISD::MEMBARRIER: return "MemBarrier";
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case ISD::ATOMIC_FENCE: return "AtomicFence";
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case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap";
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case ISD::ATOMIC_SWAP: return "AtomicSwap";
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case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd";
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@ -3221,7 +3221,12 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
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}
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void SelectionDAGBuilder::visitFence(const FenceInst &I) {
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llvm_unreachable("Not implemented yet");
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DebugLoc dl = getCurDebugLoc();
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SDValue Ops[3];
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Ops[0] = getRoot();
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Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
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Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
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DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
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}
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/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
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@ -601,9 +601,11 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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// membarrier needs custom lowering; the rest are legal and handled
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// normally.
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
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setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
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} else {
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// Set them all for expansion, which will force libcalls.
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
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setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
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setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
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setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
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@ -2277,6 +2279,33 @@ static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
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DAG.getConstant(DMBOpt, MVT::i32));
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}
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static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
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const ARMSubtarget *Subtarget) {
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// FIXME: handle "fence singlethread" more efficiently.
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DebugLoc dl = Op.getDebugLoc();
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if (!Subtarget->hasDataBarrier()) {
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// Some ARMv6 cpus can support data barriers with an mcr instruction.
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// Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
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// here.
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assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
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"Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
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return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
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DAG.getConstant(0, MVT::i32));
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}
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AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
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cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
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ARM_MB::MemBOpt DMBOpt;
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if (FenceOrdering == Release)
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DMBOpt = ARM_MB::ISHST;
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else
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DMBOpt = ARM_MB::ISH;
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return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
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DAG.getConstant(DMBOpt, MVT::i32));
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}
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static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
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const ARMSubtarget *Subtarget) {
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// ARM pre v5TE and Thumb1 does not have preload instructions.
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@ -4834,6 +4863,7 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::BR_JT: return LowerBR_JT(Op, DAG);
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case ISD::VASTART: return LowerVASTART(Op, DAG);
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case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
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case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
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case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
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@ -607,6 +607,8 @@ def : Pat<(membarrier (i64 imm), (i64 imm), (i64 imm), (i64 1), (i64 imm)),
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def : Pat<(membarrier (i64 imm), (i64 imm), (i64 imm), (i64 imm), (i64 imm)),
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(MB)>;
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def : Pat<(atomic_fence (imm), (imm)), (MB)>;
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//Basic Floating point ops
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//Floats
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@ -99,6 +99,7 @@ BlackfinTargetLowering::BlackfinTargetLowering(TargetMachine &TM)
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// Blackfin has no intrinsics for these particular operations.
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
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setOperationAction(ISD::BSWAP, MVT::i32, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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@ -174,6 +174,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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// SPU has no intrinsics for these particular operations:
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
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// SPU has no division/remainder instructions
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setOperationAction(ISD::SREM, MVT::i8, Expand);
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@ -877,6 +877,9 @@ def : Pat<(zextloadi8 xaddr:$addr), (i32 (LBU xaddr:$addr))>;
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// Peepholes
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def : Pat<(store (i32 0), iaddr:$dst), (SWI (i32 R0), iaddr:$dst)>;
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// Atomic fence
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def : Pat<(atomic_fence (imm), (imm)), (MEMBARRIER)>;
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//===----------------------------------------------------------------------===//
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// Floating Point Support
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//===----------------------------------------------------------------------===//
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@ -160,7 +160,9 @@ MipsTargetLowering(MipsTargetMachine &TM)
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// Use the default for now
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
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setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
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if (Subtarget->isSingleFloat())
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setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
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@ -529,6 +531,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const
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case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
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case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
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case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
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case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
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}
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return SDValue();
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}
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@ -1536,6 +1539,16 @@ SDValue MipsTargetLowering::LowerMEMBARRIER(SDValue Op,
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DAG.getConstant(SType, MVT::i32));
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}
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SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
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SelectionDAG& DAG) const {
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// FIXME: Need pseudo-fence for 'singlethread' fences
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// FIXME: Set SType for weaker fences where supported/appropriate.
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unsigned SType = 0;
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DebugLoc dl = Op.getDebugLoc();
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return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
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DAG.getConstant(SType, MVT::i32));
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}
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//===----------------------------------------------------------------------===//
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// Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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@ -131,6 +131,7 @@ namespace llvm {
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SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
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SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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@ -1472,5 +1472,7 @@ def : Pat<(membarrier (i32 imm /*ll*/),
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(i32 imm /*device*/)),
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(SYNC)>;
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def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
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include "PPCInstrAltivec.td"
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include "PPCInstr64Bit.td"
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@ -748,8 +748,10 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
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// SPARC has no intrinsics for these particular operations.
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// FIXME: There are instructions available for ATOMIC_FENCE
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// on SparcV8 and later.
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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@ -449,8 +449,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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if (Subtarget->hasXMM())
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setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
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// We may not have a libcall for MEMBARRIER so we should lower this.
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setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
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setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
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// On X86 and X86-64, atomic operations are lowered to locked instructions.
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// Locked instructions, in turn, have implicit fence semantics (all memory
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@ -9407,6 +9407,45 @@ SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
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return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
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}
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SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
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SelectionDAG &DAG) const {
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DebugLoc dl = Op.getDebugLoc();
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AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
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cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
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SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
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cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
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// The only fence that needs an instruction is a sequentially-consistent
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// cross-thread fence.
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if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
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// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
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// no-sse2). There isn't any reason to disable it if the target processor
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// supports it.
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if (Subtarget->hasSSE2() || Subtarget->is64Bit())
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return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
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SDValue Chain = Op.getOperand(0);
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SDValue Zero = DAG.getConstant(0, MVT::i32);
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SDValue Ops[] = {
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DAG.getRegister(X86::ESP, MVT::i32), // Base
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DAG.getTargetConstant(1, MVT::i8), // Scale
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DAG.getRegister(0, MVT::i32), // Index
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DAG.getTargetConstant(0, MVT::i32), // Disp
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DAG.getRegister(0, MVT::i32), // Segment.
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Zero,
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Chain
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};
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SDNode *Res =
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DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
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array_lengthof(Ops));
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return SDValue(Res, 0);
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}
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// MEMBARRIER is a compiler barrier; it codegens to a no-op.
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return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
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}
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SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
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EVT T = Op.getValueType();
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DebugLoc DL = Op.getDebugLoc();
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@ -9526,6 +9565,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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default: llvm_unreachable("Should not custom lower this!");
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case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
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case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
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case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
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case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
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case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
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case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
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@ -9849,6 +9889,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
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case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
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case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
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case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
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}
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}
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@ -829,6 +829,7 @@ namespace llvm {
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SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
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// Utility functions to help LowerVECTOR_SHUFFLE
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