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Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140971 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2011-10-02 16:56:09 +00:00
parent 11357d4f40
commit 146c6d77f0
2 changed files with 42 additions and 2 deletions
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41
lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
View File

@ -58,8 +58,8 @@ static InstructionContext contextForAttrs(uint8_t attrMask) {
* @return - TRUE if the ModR/M byte is required, FALSE otherwise.
*/
static int modRMRequired(OpcodeType type,
InstructionContext insnContext,
uint8_t opcode) {
InstructionContext insnContext,
uint8_t opcode) {
const struct ContextDecision* decision = 0;
switch (type) {
@ -885,6 +885,43 @@ static int getID(struct InternalInstruction* insn) {
}
return 0;
}
if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 &&
insn->rexPrefix & 0x01) {
/*
* NOOP shouldn't decode as NOOP if REX.b is set. Instead
* it should decode as XCHG %r8, %eax.
*/
const struct InstructionSpecifier *spec;
uint16_t instructionIDWithNewOpcode;
const struct InstructionSpecifier *specWithNewOpcode;
spec = specifierForUID(instructionID);
// Borrow opcode from one of the other XCHGar opcodes
insn->opcode = 0x91;
if (getIDWithAttrMask(&instructionIDWithNewOpcode,
insn,
attrMask)) {
insn->opcode = 0x90;
insn->instructionID = instructionID;
insn->spec = spec;
return 0;
}
specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode);
// Change back
insn->opcode = 0x90;
insn->instructionID = instructionIDWithNewOpcode;
insn->spec = specWithNewOpcode;
return 0;
}
insn->instructionID = instructionID;
insn->spec = specifierForUID(insn->instructionID);

3
test/MC/Disassembler/X86/simple-tests.txt
View File

@ -308,3 +308,6 @@
# CHECK: invvpid (%rax), %rax
0x66 0x0f 0x38 0x81 0x00
# CHECK: xchgl %r8d, %eax
0x41 0x90