6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-20 09:30:43 +00:00
Code Issues Projects Releases Wiki Activity

Codegen CopyFromReg using the regclass that matches the valuetype of the

Browse Source 
destination vreg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23586 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-10-02 06:34:16 +00:00
parent a916dd8888
commit 14765be0bc
1 changed files with 11 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -1031,11 +1031,11 @@ void SimpleSched::EmitNode(NodeInfo *NI) {
if (MRegisterInfo::isVirtualRegister(SrcReg)) {
TRC = RegMap->getRegClass(SrcReg);
} else {
// FIXME: we don't know what register class to generate this for. Do
// a brute force search and pick the first match. :(
// Pick the register class of the right type that contains this physreg.
for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
E = MRI.regclass_end(); I != E; ++I)
if ((*I)->contains(SrcReg)) {
if ((*I)->getType() == Node->getValueType(0) &&
(*I)->contains(SrcReg)) {
TRC = *I;
break;
}
@ -1100,7 +1100,8 @@ unsigned SimpleSched::EmitDAG(SDOperand Op) {
Op.getOperand(i).getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
MI->addRegOperand(EmitDAG(Op.getOperand(i)), MachineOperand::Use);
unsigned VReg = EmitDAG(Op.getOperand(i));
MI->addRegOperand(VReg, MachineOperand::Use);
} else if (ConstantSDNode *C =
dyn_cast<ConstantSDNode>(Op.getOperand(i))) {
MI->addZeroExtImm64Operand(C->getValue());
@ -1126,7 +1127,8 @@ unsigned SimpleSched::EmitDAG(SDOperand Op) {
assert(Op.getOperand(i).getValueType() != MVT::Other &&
Op.getOperand(i).getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
MI->addRegOperand(EmitDAG(Op.getOperand(i)), MachineOperand::Use);
unsigned VReg = EmitDAG(Op.getOperand(i));
MI->addRegOperand(VReg, MachineOperand::Use);
}
}
@ -1188,11 +1190,11 @@ unsigned SimpleSched::EmitDAG(SDOperand Op) {
if (MRegisterInfo::isVirtualRegister(SrcReg)) {
TRC = RegMap->getRegClass(SrcReg);
} else {
// FIXME: we don't know what register class to generate this for. Do
// a brute force search and pick the first match. :(
// Pick the register class of the right type that contains this physreg.
for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
E = MRI.regclass_end(); I != E; ++I)
if ((*I)->contains(SrcReg)) {
if ((*I)->getType() == Op.Val->getValueType(0) &&
(*I)->contains(SrcReg)) {
TRC = *I;
break;
}