mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
Add AVX ld/st XCSR register.
Add VEX encoding bits for MRMXm x86 form git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107204 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
1e4782d6f9
commit
147b7cad2f
@ -2019,6 +2019,8 @@ defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
|
|||||||
defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
|
defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
|
||||||
sse1_fp_unop_p<0x53, "rcp", X86frcp, int_x86_sse_rcp_ps>;
|
sse1_fp_unop_p<0x53, "rcp", X86frcp, int_x86_sse_rcp_ps>;
|
||||||
|
|
||||||
|
// There is no f64 version of the reciprocal approximation instructions.
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
// SSE 1 & 2 - Non-temporal stores
|
// SSE 1 & 2 - Non-temporal stores
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
@ -2111,7 +2113,7 @@ def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
|
|||||||
TB, Requires<[HasSSE2]>;
|
TB, Requires<[HasSSE2]>;
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
// SSE 1 & 2 - Misc Instructions
|
// SSE 1 & 2 - Misc Instructions (No AVX form)
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
// Prefetch intrinsic.
|
// Prefetch intrinsic.
|
||||||
@ -2128,12 +2130,6 @@ def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
|
|||||||
def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
|
def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
|
||||||
TB, Requires<[HasSSE1]>;
|
TB, Requires<[HasSSE1]>;
|
||||||
|
|
||||||
// MXCSR register
|
|
||||||
def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
|
|
||||||
"ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
|
|
||||||
def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
|
|
||||||
"stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
|
|
||||||
|
|
||||||
// Alias instructions that map zero vector to pxor / xorp* for sse.
|
// Alias instructions that map zero vector to pxor / xorp* for sse.
|
||||||
// We set canFoldAsLoad because this can be converted to a constant-pool
|
// We set canFoldAsLoad because this can be converted to a constant-pool
|
||||||
// load of an all-zeros value if folding it would be beneficial.
|
// load of an all-zeros value if folding it would be beneficial.
|
||||||
@ -2156,13 +2152,26 @@ def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
|
|||||||
def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
|
def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
|
||||||
(f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
|
(f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
|
||||||
|
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
// SSE 1 & 2 - Load/Store XCSR register
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
|
let isAsmParserOnly = 1 in {
|
||||||
|
def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
|
||||||
|
"ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
|
||||||
|
def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
|
||||||
|
"stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
|
||||||
|
}
|
||||||
|
|
||||||
|
def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
|
||||||
|
"ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
|
||||||
|
def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
|
||||||
|
"stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
|
||||||
|
|
||||||
//===---------------------------------------------------------------------===//
|
//===---------------------------------------------------------------------===//
|
||||||
// SSE2 Instructions
|
// SSE2 Instructions
|
||||||
//===---------------------------------------------------------------------===//
|
//===---------------------------------------------------------------------===//
|
||||||
|
|
||||||
|
|
||||||
// There is no f64 version of the reciprocal approximation instructions.
|
|
||||||
|
|
||||||
//===---------------------------------------------------------------------===//
|
//===---------------------------------------------------------------------===//
|
||||||
// SSE integer instructions
|
// SSE integer instructions
|
||||||
let ExeDomain = SSEPackedInt in {
|
let ExeDomain = SSEPackedInt in {
|
||||||
|
@ -455,15 +455,17 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
|
|||||||
unsigned NumOps = MI.getNumOperands();
|
unsigned NumOps = MI.getNumOperands();
|
||||||
unsigned CurOp = 0;
|
unsigned CurOp = 0;
|
||||||
|
|
||||||
if ((TSFlags & X86II::FormMask) == X86II::MRMDestMem)
|
|
||||||
NumOps = CurOp = X86AddrNumOperands;
|
|
||||||
|
|
||||||
switch (TSFlags & X86II::FormMask) {
|
switch (TSFlags & X86II::FormMask) {
|
||||||
case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
|
case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
|
||||||
case X86II::MRMSrcMem:
|
case X86II::MRM0m: case X86II::MRM1m:
|
||||||
|
case X86II::MRM2m: case X86II::MRM3m:
|
||||||
|
case X86II::MRM4m: case X86II::MRM5m:
|
||||||
|
case X86II::MRM6m: case X86II::MRM7m:
|
||||||
case X86II::MRMDestMem:
|
case X86II::MRMDestMem:
|
||||||
|
NumOps = CurOp = X86AddrNumOperands;
|
||||||
|
case X86II::MRMSrcMem:
|
||||||
case X86II::MRMSrcReg:
|
case X86II::MRMSrcReg:
|
||||||
if (MI.getOperand(CurOp).isReg() &&
|
if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() &&
|
||||||
X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
|
X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
|
||||||
VEX_R = 0x0;
|
VEX_R = 0x0;
|
||||||
|
|
||||||
|
@ -10950,3 +10950,19 @@
|
|||||||
// CHECK: encoding: [0xc5,0xf8,0x2b,0x08]
|
// CHECK: encoding: [0xc5,0xf8,0x2b,0x08]
|
||||||
vmovntps %xmm1, (%eax)
|
vmovntps %xmm1, (%eax)
|
||||||
|
|
||||||
|
// CHECK: vldmxcsr (%eax)
|
||||||
|
// CHECK: encoding: [0xc5,0xf8,0xae,0x10]
|
||||||
|
vldmxcsr (%eax)
|
||||||
|
|
||||||
|
// CHECK: vstmxcsr (%eax)
|
||||||
|
// CHECK: encoding: [0xc5,0xf8,0xae,0x18]
|
||||||
|
vstmxcsr (%eax)
|
||||||
|
|
||||||
|
// CHECK: vldmxcsr 3735928559
|
||||||
|
// CHECK: encoding: [0xc5,0xf8,0xae,0x15,0xef,0xbe,0xad,0xde]
|
||||||
|
vldmxcsr 0xdeadbeef
|
||||||
|
|
||||||
|
// CHECK: vstmxcsr 3735928559
|
||||||
|
// CHECK: encoding: [0xc5,0xf8,0xae,0x1d,0xef,0xbe,0xad,0xde]
|
||||||
|
vstmxcsr 0xdeadbeef
|
||||||
|
|
||||||
|
@ -998,3 +998,11 @@ pshufb CPI1_0(%rip), %xmm1
|
|||||||
// CHECK: encoding: [0xc5,0x78,0x2b,0x18]
|
// CHECK: encoding: [0xc5,0x78,0x2b,0x18]
|
||||||
vmovntps %xmm11, (%rax)
|
vmovntps %xmm11, (%rax)
|
||||||
|
|
||||||
|
// CHECK: vldmxcsr -4(%rip)
|
||||||
|
// CHECK: encoding: [0xc5,0xf8,0xae,0x15,0xfc,0xff,0xff,0xff]
|
||||||
|
vldmxcsr -4(%rip)
|
||||||
|
|
||||||
|
// CHECK: vstmxcsr -4(%rsp)
|
||||||
|
// CHECK: encoding: [0xc5,0xf8,0xae,0x5c,0x24,0xfc]
|
||||||
|
vstmxcsr -4(%rsp)
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user