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https://github.com/c64scene-ar/llvm-6502.git
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x86 vector shuffle lowering now relies only on target specific
nodes to emit shuffles and don't do isel mask matching anymore. - Add the selection of the remaining shuffle opcode (movddup) - Introduce two new functions to "recognize" where we may get potential folds and add several comments to them explaining why they are not yet in the desidered shape. - Add more patterns to fallback the case where we select a specific shuffle opcode as if it could fold a load, but it can't, so remap to a valid instruction. - Add a couple of FIXMEs to address in the following days once there's a good solution to the current folding problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113369 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2604,6 +2604,7 @@ static bool isTargetShuffle(unsigned Opcode) {
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case X86ISD::MOVLPD:
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case X86ISD::MOVLPD:
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case X86ISD::MOVSHDUP:
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case X86ISD::MOVSHDUP:
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case X86ISD::MOVSLDUP:
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case X86ISD::MOVSLDUP:
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case X86ISD::MOVDDUP:
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case X86ISD::MOVSS:
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case X86ISD::MOVSS:
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case X86ISD::MOVSD:
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case X86ISD::MOVSD:
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case X86ISD::UNPCKLPS:
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case X86ISD::UNPCKLPS:
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@ -2629,6 +2630,7 @@ static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
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default: llvm_unreachable("Unknown x86 shuffle node");
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default: llvm_unreachable("Unknown x86 shuffle node");
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case X86ISD::MOVSHDUP:
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case X86ISD::MOVSHDUP:
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case X86ISD::MOVSLDUP:
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case X86ISD::MOVSLDUP:
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case X86ISD::MOVDDUP:
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return DAG.getNode(Opc, dl, VT, V1);
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return DAG.getNode(Opc, dl, VT, V1);
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}
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}
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@ -3645,9 +3647,6 @@ static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
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/// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32.
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/// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32.
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static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
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static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
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if (SV->getValueType(0).getVectorNumElements() <= 4)
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return SDValue(SV, 0);
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EVT PVT = MVT::v4f32;
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EVT PVT = MVT::v4f32;
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EVT VT = SV->getValueType(0);
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EVT VT = SV->getValueType(0);
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DebugLoc dl = SV->getDebugLoc();
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DebugLoc dl = SV->getDebugLoc();
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@ -5138,6 +5137,98 @@ static bool MayFoldVectorLoad(SDValue V) {
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return false;
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return false;
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}
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}
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// FIXME: the version above should always be used. Since there's
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// a bug where several vector shuffles can't be folded because the
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// DAG is not updated during lowering and a node claims to have two
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// uses while it only has one, use this version, and let isel match
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// another instruction if the load really happens to have more than
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// one use. Remove this version after this bug get fixed.
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static bool RelaxedMayFoldVectorLoad(SDValue V) {
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if (V.hasOneUse() && V.getOpcode() == ISD::BIT_CONVERT)
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V = V.getOperand(0);
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if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
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V = V.getOperand(0);
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if (ISD::isNormalLoad(V.getNode()))
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return true;
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return false;
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}
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/// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
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/// a vector extract, and if both can be later optimized into a single load.
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/// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
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/// here because otherwise a target specific shuffle node is going to be
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/// emitted for this shuffle, and the optimization not done.
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/// FIXME: This is probably not the best approach, but fix the problem
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/// until the right path is decided.
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static
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bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
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const TargetLowering &TLI) {
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EVT VT = V.getValueType();
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ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
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// Be sure that the vector shuffle is present in a pattern like this:
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// (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
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if (!V.hasOneUse())
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return false;
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SDNode *N = *V.getNode()->use_begin();
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if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
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return false;
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SDValue EltNo = N->getOperand(1);
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if (!isa<ConstantSDNode>(EltNo))
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return false;
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// If the bit convert changed the number of elements, it is unsafe
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// to examine the mask.
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bool HasShuffleIntoBitcast = false;
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if (V.getOpcode() == ISD::BIT_CONVERT) {
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EVT SrcVT = V.getOperand(0).getValueType();
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if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
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return false;
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V = V.getOperand(0);
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HasShuffleIntoBitcast = true;
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}
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// Select the input vector, guarding against out of range extract vector.
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unsigned NumElems = VT.getVectorNumElements();
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unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
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int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
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V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
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// Skip one more bit_convert if necessary
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if (V.getOpcode() == ISD::BIT_CONVERT)
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V = V.getOperand(0);
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if (ISD::isNormalLoad(V.getNode())) {
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// Is the original load suitable?
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LoadSDNode *LN0 = cast<LoadSDNode>(V);
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// FIXME: avoid the multi-use bug that is preventing lots of
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// of foldings to be detected, this is still wrong of course, but
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// give the temporary desired behavior, and if it happens that
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// the load has real more uses, during isel it will not fold, and
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// will generate poor code.
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if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
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return false;
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if (!HasShuffleIntoBitcast)
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return true;
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// If there's a bitcast before the shuffle, check if the load type and
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// alignment is valid.
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unsigned Align = LN0->getAlignment();
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unsigned NewAlign =
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TLI.getTargetData()->getABITypeAlignment(
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VT.getTypeForEVT(*DAG.getContext()));
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if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
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return false;
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}
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return true;
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}
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static
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static
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SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
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SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
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bool HasSSE2) {
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bool HasSSE2) {
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@ -5253,6 +5344,7 @@ static inline unsigned getUNPCKHOpcode(EVT VT) {
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static
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static
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SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
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SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
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const TargetLowering &TLI,
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const X86Subtarget *Subtarget) {
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const X86Subtarget *Subtarget) {
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
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EVT VT = Op.getValueType();
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EVT VT = Op.getValueType();
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@ -5263,9 +5355,23 @@ SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
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if (isZeroShuffle(SVOp))
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if (isZeroShuffle(SVOp))
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return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
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return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
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// Promote splats to v4f32.
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// Handle splat operations
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if (SVOp->isSplat())
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if (SVOp->isSplat()) {
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// Special case, this is the only place now where it's
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// allowed to return a vector_shuffle operation without
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// using a target specific node, because *hopefully* it
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// will be optimized away by the dag combiner.
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if (VT.getVectorNumElements() <= 4 &&
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CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
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return Op;
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// Handle splats by matching through known masks
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if (VT.getVectorNumElements() <= 4)
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return SDValue();
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// Canonize all of the remaining to v4f32.
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return PromoteSplat(SVOp, DAG);
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return PromoteSplat(SVOp, DAG);
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}
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// If the shuffle can be profitably rewritten as a narrower shuffle, then
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// If the shuffle can be profitably rewritten as a narrower shuffle, then
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// do it!
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// do it!
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@ -5336,7 +5442,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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// Normalize the input vectors. Here splats, zeroed vectors, profitable
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// Normalize the input vectors. Here splats, zeroed vectors, profitable
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// narrowing and commutation of operands should be handled. The actual code
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// narrowing and commutation of operands should be handled. The actual code
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// doesn't include all of those, work in progress...
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// doesn't include all of those, work in progress...
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SDValue NewOp = NormalizeVectorShuffle(Op, DAG, Subtarget);
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SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
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if (NewOp.getNode())
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if (NewOp.getNode())
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return NewOp;
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return NewOp;
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@ -5349,6 +5455,18 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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if (VT != MVT::v2i64 && VT != MVT::v2f64)
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if (VT != MVT::v2i64 && VT != MVT::v2f64)
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return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
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return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
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if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
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RelaxedMayFoldVectorLoad(V1) && !isMMX)
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return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
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if (!isMMX && X86::isMOVHLPS_v_undef_Mask(SVOp))
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return getMOVHighToLow(Op, dl, DAG);
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// Use to match splats
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if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
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(VT == MVT::v2f64 || VT == MVT::v2i64))
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return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
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if (X86::isPSHUFDMask(SVOp)) {
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if (X86::isPSHUFDMask(SVOp)) {
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// The actual implementation will match the mask in the if above and then
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// The actual implementation will match the mask in the if above and then
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// during isel it can match several different instructions, not only pshufd
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// during isel it can match several different instructions, not only pshufd
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@ -5820,6 +5820,14 @@ def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
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(MOVLHPSrr VR128:$src1, VR128:$src2)>;
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(MOVLHPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
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def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
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(MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
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(MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
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// FIXME: Instead of X86Movddup, there should be a X86Movlhps here, the problem
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// is during lowering, where it's not possible to recognize the load fold cause
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// it has two uses through a bitcast. One use disappears at isel time and the
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// fold opportunity reappears.
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def : Pat<(v2i64 (X86Movddup VR128:$src)),
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(MOVLHPSrr VR128:$src, VR128:$src)>;
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def : Pat<(v4f32 (X86Movddup VR128:$src)),
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(MOVLHPSrr VR128:$src, VR128:$src)>;
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// Shuffle with MOVLHPD
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// Shuffle with MOVLHPD
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def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
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def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
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