6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 20:32:21 +00:00
Code Issues Projects Releases Wiki Activity

Teach ComputeMaskedBits about sub nsw.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127548 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2011-03-12 17:18:11 +00:00
parent 879d3a98a2
commit 14b2a59301
2 changed files with 39 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
lib/Analysis/ValueTracking.cpp
View File

@ -431,16 +431,24 @@ void llvm::ComputeMaskedBits(Value *V, const APInt &Mask,
}
// Are we still trying to solve for the sign bit?
if (I->getOpcode() == Instruction::Add &&
Mask.isNegative() && !KnownZero.isNegative() && !KnownOne.isNegative()){
if (Mask.isNegative() && !KnownZero.isNegative() && !KnownOne.isNegative()){
OverflowingBinaryOperator *OBO = cast<OverflowingBinaryOperator>(I);
if (OBO->hasNoSignedWrap()) {
// Adding two positive numbers can't wrap into negative ...
if (LHSKnownZero.isNegative() && KnownZero2.isNegative())
KnownZero |= APInt::getSignBit(BitWidth);
// and adding two negative numbers can't wrap into positive.
else if (LHSKnownOne.isNegative() && KnownOne2.isNegative())
KnownOne |= APInt::getSignBit(BitWidth);
if (I->getOpcode() == Instruction::Add) {
// Adding two positive numbers can't wrap into negative
if (LHSKnownZero.isNegative() && KnownZero2.isNegative())
KnownZero |= APInt::getSignBit(BitWidth);
// and adding two negative numbers can't wrap into positive.
else if (LHSKnownOne.isNegative() && KnownOne2.isNegative())
KnownOne |= APInt::getSignBit(BitWidth);
} else {
// Subtracting a negative number from a positive one can't wrap
if (LHSKnownZero.isNegative() && KnownOne2.isNegative())
KnownZero |= APInt::getSignBit(BitWidth);
// neither can subtracting a positive number from a negative one.
else if (LHSKnownOne.isNegative() && KnownZero2.isNegative())
KnownOne |= APInt::getSignBit(BitWidth);
}
}
}

23
test/Transforms/InstSimplify/compare.ll
View File

@ -271,6 +271,29 @@ define i1 @srem2(i16 %X, i32 %Y) {
%D = icmp slt i32 %C, 0
ret i1 %D
}
; CHECK: @srem3
; CHECK-NEXT: ret i1 false
define i1 @srem3(i16 %X, i32 %Y) {
%A = zext i16 %X to i32
%B = or i32 2147483648, %A
%C = sub nsw i32 1, %B
%D = srem i32 %C, %Y
%E = icmp slt i32 %D, 0
ret i1 %E
}
; CHECK: @srem4
; CHECK-NEXT: ret i1 false
define i1 @srem4(i16 %X, i32 %Y) {
%A = zext i16 %X to i32
%B = or i32 2147483648, %A
%C = sub nsw i32 %A, %B
%D = srem i32 %C, %Y
%E = icmp slt i32 %D, 0
ret i1 %E
}
define i1 @udiv1(i32 %X) {
; CHECK: @udiv1
%A = udiv i32 %X, 1000000