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https://github.com/c64scene-ar/llvm-6502.git
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Add more fused mul+add/sub patterns. rdar://10139676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154484 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
e611378a6e
commit
14b4c03580
@ -4133,12 +4133,18 @@ def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32",
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Requires<[HasVFP4,UseFusedMAC]>;
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// Match @llvm.fma.* intrinsics
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def : Pat<(fma (v2f32 DPR:$src1), (v2f32 DPR:$Vn), (v2f32 DPR:$Vm)),
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def : Pat<(v2f32 (fma DPR:$src1, DPR:$Vn, DPR:$Vm)),
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(VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
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Requires<[HasVFP4]>;
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def : Pat<(fma (v4f32 QPR:$src1), (v4f32 QPR:$Vn), (v4f32 QPR:$Vm)),
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def : Pat<(v4f32 (fma QPR:$src1, QPR:$Vn, QPR:$Vm)),
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(VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
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Requires<[HasVFP4]>;
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def : Pat<(v2f32 (fma (fneg DPR:$src1), DPR:$Vn, DPR:$Vm)),
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(VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
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Requires<[HasVFP4]>;
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def : Pat<(v4f32 (fma (fneg QPR:$src1), QPR:$Vn, QPR:$Vm)),
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(VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
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Requires<[HasVFP4]>;
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// Vector Subtract Operations.
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@ -1081,10 +1081,10 @@ def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
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Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
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// Match @llvm.fma.* intrinsics
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def : Pat<(fma (f64 DPR:$Ddin), (f64 DPR:$Dn), (f64 DPR:$Dm)),
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def : Pat<(f64 (fma DPR:$Ddin, DPR:$Dn, DPR:$Dm)),
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(VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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Requires<[HasVFP4]>;
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def : Pat<(fma (f32 SPR:$Sdin), (f32 SPR:$Sn), (f32 SPR:$Sm)),
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def : Pat<(f32 (fma SPR:$Sdin, SPR:$Sn, SPR:$Sm)),
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(VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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Requires<[HasVFP4]>;
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@ -1114,6 +1114,22 @@ def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
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(VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
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Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
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// Match @llvm.fma.* intrinsics
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// (fma (fneg x), y, z) -> (vfms x, y, z)
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def : Pat<(f64 (fma (fneg DPR:$Ddin), DPR:$Dn, DPR:$Dm)),
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(VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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Requires<[HasVFP4]>;
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def : Pat<(f32 (fma (fneg SPR:$Sdin), SPR:$Sn, SPR:$Sm)),
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(VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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Requires<[HasVFP4]>;
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// (fneg (fma x, (fneg y), z) -> (vfms x, y, z)
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def : Pat<(fneg (f64 (fma DPR:$Ddin, (fneg DPR:$Dn), DPR:$Dm))),
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(VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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Requires<[HasVFP4]>;
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def : Pat<(fneg (f32 (fma SPR:$Sdin, (fneg SPR:$Sn), SPR:$Sm))),
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(VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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Requires<[HasVFP4]>;
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def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
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(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
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IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
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@ -1141,12 +1157,20 @@ def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
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Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
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// Match @llvm.fma.* intrinsics
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// (fneg (fma x, y, z)) -> (vfnma x, y, z)
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def : Pat<(fneg (fma (f64 DPR:$Ddin), (f64 DPR:$Dn), (f64 DPR:$Dm))),
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(VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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Requires<[HasVFP4]>;
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def : Pat<(fneg (fma (f32 SPR:$Sdin), (f32 SPR:$Sn), (f32 SPR:$Sm))),
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(VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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Requires<[HasVFP4]>;
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// (fma (fneg x), y, (fneg z)) -> (vfnma x, y, z)
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def : Pat<(f64 (fma (fneg DPR:$Ddin), DPR:$Dn, (fneg DPR:$Dm))),
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(VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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Requires<[HasVFP4]>;
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def : Pat<(f32 (fma (fneg SPR:$Sdin), SPR:$Sn, (fneg SPR:$Sm))),
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(VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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Requires<[HasVFP4]>;
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def VFNMSD : ADbI<0b11101, 0b01, 0, 0,
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(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
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@ -1173,6 +1197,22 @@ def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
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(VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
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Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
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// Match @llvm.fma.* intrinsics
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// (fneg (fma (fneg x), y, z)) -> (vnfms x, y, z)
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def : Pat<(fneg (f64 (fma (fneg DPR:$Ddin), DPR:$Dn, DPR:$Dm))),
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(VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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Requires<[HasVFP4]>;
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def : Pat<(fneg (f32 (fma (fneg SPR:$Sdin), SPR:$Sn, SPR:$Sm))),
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(VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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Requires<[HasVFP4]>;
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// (fma x, (fneg y), z) -> (vnfms x, y, z)
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def : Pat<(f64 (fma DPR:$Ddin, (fneg DPR:$Dn), DPR:$Dm)),
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(VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
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Requires<[HasVFP4]>;
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def : Pat<(f32 (fma SPR:$Sdin, (fneg SPR:$Sn), SPR:$Sm)),
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(VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
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Requires<[HasVFP4]>;
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//===----------------------------------------------------------------------===//
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// FP Conditional moves.
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//
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@ -103,43 +103,81 @@ define float @test_fma_f32(float %a, float %b, float %c) nounwind readnone ssp {
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entry:
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; CHECK: test_fma_f32
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; CHECK: vfma.f32
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%call = tail call float @llvm.fma.f32(float %a, float %b, float %c) nounwind readnone
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ret float %call
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%tmp1 = tail call float @llvm.fma.f32(float %a, float %b, float %c) nounwind readnone
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ret float %tmp1
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}
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define double @test_fma_f64(double %a, double %b, double %c) nounwind readnone ssp {
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entry:
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; CHECK: test_fma_f64
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; CHECK: vfma.f64
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%call = tail call double @llvm.fma.f64(double %a, double %b, double %c) nounwind readnone
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ret double %call
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%tmp1 = tail call double @llvm.fma.f64(double %a, double %b, double %c) nounwind readnone
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ret double %tmp1
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}
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define <2 x float> @test_fma_v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind readnone ssp {
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entry:
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; CHECK: test_fma_v2f32
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; CHECK: vfma.f32
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%0 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind
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ret <2 x float> %0
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%tmp1 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind
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ret <2 x float> %tmp1
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}
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define float @test_fnma_f32(float %a, float %b, float %c) nounwind readnone ssp {
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define double @test_fms_f64(double %a, double %b, double %c) nounwind readnone ssp {
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entry:
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; CHECK: test_fnma_f32
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; CHECK: vfnma.f32
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%call = tail call float @llvm.fma.f32(float %a, float %b, float %c) nounwind readnone
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%tmp1 = fsub float -0.0, %call
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%tmp2 = fsub float %tmp1, %c
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ret float %tmp2
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; CHECK: test_fms_f64
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; CHECK: vfms.f64
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%tmp1 = fsub double -0.0, %a
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%tmp2 = tail call double @llvm.fma.f64(double %tmp1, double %b, double %c) nounwind readnone
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ret double %tmp2
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}
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define double @test_fms_f64_2(double %a, double %b, double %c) nounwind readnone ssp {
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entry:
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; CHECK: test_fms_f64_2
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; CHECK: vfms.f64
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%tmp1 = fsub double -0.0, %b
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%tmp2 = tail call double @llvm.fma.f64(double %a, double %tmp1, double %c) nounwind readnone
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%tmp3 = fsub double -0.0, %tmp2
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ret double %tmp3
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}
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define double @test_fnms_f64(double %a, double %b, double %c) nounwind readnone ssp {
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entry:
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; CHECK: test_fnms_f64
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; CHECK: vfnms.f64
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%tmp1 = fsub double -0.0, %a
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%tmp2 = tail call double @llvm.fma.f64(double %tmp1, double %b, double %c) nounwind readnone
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%tmp3 = fsub double -0.0, %tmp2
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ret double %tmp3
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}
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define double @test_fnms_f64_2(double %a, double %b, double %c) nounwind readnone ssp {
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entry:
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; CHECK: test_fnms_f64_2
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; CHECK: vfnms.f64
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%tmp1 = fsub double -0.0, %b
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%tmp2 = tail call double @llvm.fma.f64(double %a, double %tmp1, double %c) nounwind readnone
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ret double %tmp2
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}
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define double @test_fnma_f64(double %a, double %b, double %c) nounwind readnone ssp {
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entry:
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; CHECK: test_fnma_f64
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; CHECK: vfnma.f64
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%call = tail call double @llvm.fma.f64(double %a, double %b, double %c) nounwind readnone
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%tmp = fsub double -0.0, %call
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ret double %tmp
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%tmp1 = tail call double @llvm.fma.f64(double %a, double %b, double %c) nounwind readnone
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%tmp2 = fsub double -0.0, %tmp1
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ret double %tmp2
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}
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define double @test_fnma_f64_2(double %a, double %b, double %c) nounwind readnone ssp {
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entry:
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; CHECK: test_fnma_f64_2
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; CHECK: vfnma.f64
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%tmp1 = fsub double -0.0, %a
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%tmp2 = fsub double -0.0, %c
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%tmp3 = tail call double @llvm.fma.f64(double %tmp1, double %b, double %tmp2) nounwind readnone
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ret double %tmp3
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}
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declare float @llvm.fma.f32(float, float, float) nounwind readnone
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