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https://github.com/c64scene-ar/llvm-6502.git
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Revert "[FastISel][AArch64] Add support for more addressing modes."
This reverts commits r215597, because it might have broken the build bots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215659 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
parent
b1b9953473
commit
14bc045838
@ -41,6 +41,7 @@ using namespace llvm;
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namespace {
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class AArch64FastISel : public FastISel {
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class Address {
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public:
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typedef enum {
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@ -50,23 +51,17 @@ class AArch64FastISel : public FastISel {
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private:
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BaseKind Kind;
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AArch64_AM::ShiftExtendType ExtType;
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union {
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unsigned Reg;
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int FI;
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} Base;
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unsigned OffsetReg;
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unsigned Shift;
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int64_t Offset;
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const GlobalValue *GV;
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public:
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Address() : Kind(RegBase), ExtType(AArch64_AM::InvalidShiftExtend),
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OffsetReg(0), Shift(0), Offset(0), GV(nullptr) { Base.Reg = 0; }
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Address() : Kind(RegBase), Offset(0), GV(nullptr) { Base.Reg = 0; }
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void setKind(BaseKind K) { Kind = K; }
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BaseKind getKind() const { return Kind; }
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void setExtendType(AArch64_AM::ShiftExtendType E) { ExtType = E; }
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AArch64_AM::ShiftExtendType getExtendType() const { return ExtType; }
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bool isRegBase() const { return Kind == RegBase; }
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bool isFIBase() const { return Kind == FrameIndexBase; }
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void setReg(unsigned Reg) {
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@ -77,14 +72,6 @@ class AArch64FastISel : public FastISel {
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assert(isRegBase() && "Invalid base register access!");
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return Base.Reg;
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}
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void setOffsetReg(unsigned Reg) {
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assert(isRegBase() && "Invalid offset register access!");
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OffsetReg = Reg;
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}
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unsigned getOffsetReg() const {
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assert(isRegBase() && "Invalid offset register access!");
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return OffsetReg;
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}
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void setFI(unsigned FI) {
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assert(isFIBase() && "Invalid base frame index access!");
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Base.FI = FI;
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@ -95,11 +82,11 @@ class AArch64FastISel : public FastISel {
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}
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void setOffset(int64_t O) { Offset = O; }
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int64_t getOffset() { return Offset; }
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void setShift(unsigned S) { Shift = S; }
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unsigned getShift() { return Shift; }
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void setGlobalValue(const GlobalValue *G) { GV = G; }
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const GlobalValue *getGlobalValue() { return GV; }
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bool isValid() { return isFIBase() || (isRegBase() && getReg() != 0); }
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};
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/// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
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@ -134,12 +121,13 @@ private:
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// Utility helper routines.
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bool isTypeLegal(Type *Ty, MVT &VT);
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bool isLoadStoreTypeLegal(Type *Ty, MVT &VT);
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bool ComputeAddress(const Value *Obj, Address &Addr, Type *Ty = nullptr);
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bool ComputeAddress(const Value *Obj, Address &Addr);
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bool ComputeCallAddress(const Value *V, Address &Addr);
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bool SimplifyAddress(Address &Addr, MVT VT);
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bool SimplifyAddress(Address &Addr, MVT VT, int64_t ScaleFactor,
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bool UseUnscaled);
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void AddLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
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unsigned Flags, unsigned ScaleFactor,
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MachineMemOperand *MMO);
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unsigned Flags, MachineMemOperand *MMO,
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bool UseUnscaled);
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bool IsMemCpySmall(uint64_t Len, unsigned Alignment);
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bool TryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
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unsigned Alignment);
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@ -149,9 +137,9 @@ private:
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// Emit functions.
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bool EmitCmp(Value *Src1Value, Value *Src2Value, bool isZExt);
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bool EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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MachineMemOperand *MMO = nullptr);
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MachineMemOperand *MMO = nullptr, bool UseUnscaled = false);
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bool EmitStore(MVT VT, unsigned SrcReg, Address Addr,
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MachineMemOperand *MMO = nullptr);
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MachineMemOperand *MMO = nullptr, bool UseUnscaled = false);
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unsigned EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
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unsigned Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
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unsigned Emit_MUL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
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@ -349,8 +337,7 @@ unsigned AArch64FastISel::TargetMaterializeConstant(const Constant *C) {
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}
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// Computes the address to get to an object.
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bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr, Type *Ty)
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{
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bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr) {
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const User *U = nullptr;
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unsigned Opcode = Instruction::UserOp1;
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if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
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@ -377,18 +364,18 @@ bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr, Type *Ty)
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break;
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case Instruction::BitCast: {
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// Look through bitcasts.
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return ComputeAddress(U->getOperand(0), Addr, Ty);
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return ComputeAddress(U->getOperand(0), Addr);
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}
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case Instruction::IntToPtr: {
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// Look past no-op inttoptrs.
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if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
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return ComputeAddress(U->getOperand(0), Addr, Ty);
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return ComputeAddress(U->getOperand(0), Addr);
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break;
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}
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case Instruction::PtrToInt: {
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// Look past no-op ptrtoints.
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if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
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return ComputeAddress(U->getOperand(0), Addr, Ty);
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return ComputeAddress(U->getOperand(0), Addr);
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break;
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}
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case Instruction::GetElementPtr: {
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@ -430,7 +417,7 @@ bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr, Type *Ty)
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// Try to grab the base operand now.
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Addr.setOffset(TmpOffset);
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if (ComputeAddress(U->getOperand(0), Addr, Ty))
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if (ComputeAddress(U->getOperand(0), Addr))
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return true;
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// We failed, restore everything and try the other options.
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@ -450,86 +437,19 @@ bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr, Type *Ty)
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}
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break;
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}
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case Instruction::Add: {
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case Instruction::Add:
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// Adds of constants are common and easy enough.
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const Value *LHS = U->getOperand(0);
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const Value *RHS = U->getOperand(1);
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if (isa<ConstantInt>(LHS))
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std::swap(LHS, RHS);
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if (const ConstantInt *CI = dyn_cast<ConstantInt>(RHS)) {
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if (const ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
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Addr.setOffset(Addr.getOffset() + (uint64_t)CI->getSExtValue());
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return ComputeAddress(LHS, Addr, Ty);
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}
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Address Backup = Addr;
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if (ComputeAddress(LHS, Addr, Ty) && ComputeAddress(RHS, Addr, Ty))
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return true;
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Addr = Backup;
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break;
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}
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case Instruction::Shl:
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if (Addr.getOffsetReg())
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break;
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if (const auto *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
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unsigned Val = CI->getZExtValue();
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if (Val < 1 || Val > 3)
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break;
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uint64_t NumBytes = 0;
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if (Ty && Ty->isSized()) {
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uint64_t NumBits = DL.getTypeSizeInBits(Ty);
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NumBytes = NumBits / 8;
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if (!isPowerOf2_64(NumBits))
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NumBytes = 0;
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}
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if (NumBytes != (1ULL << Val))
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break;
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Addr.setShift(Val);
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Addr.setExtendType(AArch64_AM::LSL);
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if (const auto *I = dyn_cast<Instruction>(U->getOperand(0)))
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if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
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U = I;
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if (const auto *ZE = dyn_cast<ZExtInst>(U))
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if (ZE->getOperand(0)->getType()->isIntegerTy(32))
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Addr.setExtendType(AArch64_AM::UXTW);
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if (const auto *SE = dyn_cast<SExtInst>(U))
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if (SE->getOperand(0)->getType()->isIntegerTy(32))
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Addr.setExtendType(AArch64_AM::SXTW);
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unsigned Reg = getRegForValue(U->getOperand(0));
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if (!Reg)
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return false;
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Addr.setOffsetReg(Reg);
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return true;
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return ComputeAddress(U->getOperand(0), Addr);
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}
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break;
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}
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if (Addr.getReg()) {
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if (!Addr.getOffsetReg()) {
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unsigned Reg = getRegForValue(Obj);
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if (!Reg)
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return false;
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Addr.setOffsetReg(Reg);
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return true;
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}
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return false;
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}
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unsigned Reg = getRegForValue(Obj);
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if (!Reg)
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return false;
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Addr.setReg(Reg);
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return true;
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// Try to get this in a register if nothing else has worked.
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if (!Addr.isValid())
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Addr.setReg(getRegForValue(Obj));
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return Addr.isValid();
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}
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bool AArch64FastISel::ComputeCallAddress(const Value *V, Address &Addr) {
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@ -611,80 +531,50 @@ bool AArch64FastISel::isLoadStoreTypeLegal(Type *Ty, MVT &VT) {
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return false;
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}
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bool AArch64FastISel::SimplifyAddress(Address &Addr, MVT VT) {
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unsigned ScaleFactor;
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bool AArch64FastISel::SimplifyAddress(Address &Addr, MVT VT,
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int64_t ScaleFactor, bool UseUnscaled) {
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bool needsLowering = false;
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int64_t Offset = Addr.getOffset();
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switch (VT.SimpleTy) {
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default: return false;
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case MVT::i1: // fall-through
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case MVT::i8: ScaleFactor = 1; break;
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case MVT::i16: ScaleFactor = 2; break;
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case MVT::i32: // fall-through
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case MVT::f32: ScaleFactor = 4; break;
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case MVT::i64: // fall-through
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case MVT::f64: ScaleFactor = 8; break;
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default:
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return false;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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case MVT::f32:
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case MVT::f64:
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if (!UseUnscaled)
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// Using scaled, 12-bit, unsigned immediate offsets.
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needsLowering = ((Offset & 0xfff) != Offset);
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else
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// Using unscaled, 9-bit, signed immediate offsets.
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needsLowering = (Offset > 256 || Offset < -256);
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break;
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}
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bool ImmediateOffsetNeedsLowering = false;
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bool RegisterOffsetNeedsLowering = false;
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int64_t Offset = Addr.getOffset();
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if (((Offset < 0) || (Offset & (ScaleFactor - 1))) && !isInt<9>(Offset))
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ImmediateOffsetNeedsLowering = true;
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else if (Offset > 0 && !(Offset & (ScaleFactor - 1)) &&
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!isUInt<12>(Offset / ScaleFactor))
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ImmediateOffsetNeedsLowering = true;
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// Cannot encode an offset register and an immediate offset in the same
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// instruction. Fold the immediate offset into the load/store instruction and
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// emit an additonal add to take care of the offset register.
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if (!ImmediateOffsetNeedsLowering && Addr.getOffset() && Addr.isRegBase() &&
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Addr.getOffsetReg())
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RegisterOffsetNeedsLowering = true;
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// If this is a stack pointer and the offset needs to be simplified then put
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//If this is a stack pointer and the offset needs to be simplified then put
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// the alloca address into a register, set the base type back to register and
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// continue. This should almost never happen.
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if (ImmediateOffsetNeedsLowering && Addr.isFIBase()) {
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if (needsLowering && Addr.getKind() == Address::FrameIndexBase) {
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unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
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ResultReg)
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.addFrameIndex(Addr.getFI())
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.addImm(0)
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.addImm(0);
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.addFrameIndex(Addr.getFI())
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.addImm(0)
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.addImm(0);
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Addr.setKind(Address::RegBase);
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Addr.setReg(ResultReg);
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}
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if (RegisterOffsetNeedsLowering) {
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unsigned ResultReg = 0;
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if (Addr.getReg()) {
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ResultReg = createResultReg(&AArch64::GPR64RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(AArch64::ADDXrs), ResultReg)
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.addReg(Addr.getReg())
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.addReg(Addr.getOffsetReg())
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.addImm(Addr.getShift());
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} else
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ResultReg = Emit_LSL_ri(MVT::i64, Addr.getOffsetReg(),
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/*Op0IsKill=*/false, Addr.getShift());
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if (!ResultReg)
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return false;
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Addr.setReg(ResultReg);
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Addr.setOffsetReg(0);
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Addr.setShift(0);
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}
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// Since the offset is too large for the load/store instruction get the
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// reg+offset into a register.
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if (ImmediateOffsetNeedsLowering) {
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unsigned ResultReg = 0;
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if (Addr.getReg())
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ResultReg = FastEmit_ri_(MVT::i64, ISD::ADD, Addr.getReg(),
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/*IsKill=*/false, Offset, MVT::i64);
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else
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ResultReg = FastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset);
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if (!ResultReg)
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if (needsLowering) {
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uint64_t UnscaledOffset = Addr.getOffset() * ScaleFactor;
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unsigned ResultReg = FastEmit_ri_(MVT::i64, ISD::ADD, Addr.getReg(), false,
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UnscaledOffset, MVT::i64);
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if (ResultReg == 0)
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return false;
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Addr.setReg(ResultReg);
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Addr.setOffset(0);
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@ -695,11 +585,11 @@ bool AArch64FastISel::SimplifyAddress(Address &Addr, MVT VT) {
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void AArch64FastISel::AddLoadStoreOperands(Address &Addr,
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const MachineInstrBuilder &MIB,
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unsigned Flags,
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unsigned ScaleFactor,
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MachineMemOperand *MMO) {
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int64_t Offset = Addr.getOffset() / ScaleFactor;
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MachineMemOperand *MMO,
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bool UseUnscaled) {
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int64_t Offset = Addr.getOffset();
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// Frame base works a bit differently. Handle it separately.
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if (Addr.isFIBase()) {
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if (Addr.getKind() == Address::FrameIndexBase) {
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int FI = Addr.getFI();
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// FIXME: We shouldn't be using getObjectSize/getObjectAlignment. The size
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// and alignment should be based on the VT.
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@ -709,19 +599,9 @@ void AArch64FastISel::AddLoadStoreOperands(Address &Addr,
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// Now add the rest of the operands.
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MIB.addFrameIndex(FI).addImm(Offset);
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} else {
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assert(Addr.isRegBase() && "Unexpected address kind.");
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if (Addr.getOffsetReg()) {
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assert(Addr.getOffset() == 0 && "Unexpected offset");
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bool IsSigned = Addr.getExtendType() == AArch64_AM::SXTW ||
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Addr.getExtendType() == AArch64_AM::SXTX;
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MIB.addReg(Addr.getReg());
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MIB.addReg(Addr.getOffsetReg());
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MIB.addImm(IsSigned);
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MIB.addImm(Addr.getShift() != 0);
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} else {
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MIB.addReg(Addr.getReg());
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MIB.addImm(Offset);
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}
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// Now add the rest of the operands.
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MIB.addReg(Addr.getReg());
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MIB.addImm(Offset);
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}
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if (MMO)
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@ -729,68 +609,72 @@ void AArch64FastISel::AddLoadStoreOperands(Address &Addr,
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}
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bool AArch64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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MachineMemOperand *MMO) {
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// Simplify this down to something we can handle.
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if (!SimplifyAddress(Addr, VT))
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return false;
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unsigned ScaleFactor;
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switch (VT.SimpleTy) {
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default: llvm_unreachable("Unexpected value type.");
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case MVT::i1: // fall-through
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case MVT::i8: ScaleFactor = 1; break;
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case MVT::i16: ScaleFactor = 2; break;
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case MVT::i32: // fall-through
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case MVT::f32: ScaleFactor = 4; break;
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case MVT::i64: // fall-through
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case MVT::f64: ScaleFactor = 8; break;
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}
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MachineMemOperand *MMO, bool UseUnscaled) {
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// Negative offsets require unscaled, 9-bit, signed immediate offsets.
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// Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
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bool UseScaled = true;
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if ((Addr.getOffset() < 0) || (Addr.getOffset() & (ScaleFactor - 1))) {
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UseScaled = false;
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ScaleFactor = 1;
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}
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static const unsigned OpcTable[4][6] = {
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{ AArch64::LDURBBi, AArch64::LDURHHi, AArch64::LDURWi, AArch64::LDURXi,
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AArch64::LDURSi, AArch64::LDURDi },
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{ AArch64::LDRBBui, AArch64::LDRHHui, AArch64::LDRWui, AArch64::LDRXui,
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AArch64::LDRSui, AArch64::LDRDui },
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{ AArch64::LDRBBroX, AArch64::LDRHHroX, AArch64::LDRWroX, AArch64::LDRXroX,
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AArch64::LDRSroX, AArch64::LDRDroX },
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{ AArch64::LDRBBroW, AArch64::LDRHHroW, AArch64::LDRWroW, AArch64::LDRXroW,
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AArch64::LDRSroW, AArch64::LDRDroW }
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};
|
||||
if (!UseUnscaled && Addr.getOffset() < 0)
|
||||
UseUnscaled = true;
|
||||
|
||||
unsigned Opc;
|
||||
const TargetRegisterClass *RC;
|
||||
bool VTIsi1 = false;
|
||||
bool UseRegOffset = Addr.isRegBase() && !Addr.getOffset() && Addr.getReg() &&
|
||||
Addr.getOffsetReg();
|
||||
unsigned Idx = UseRegOffset ? 2 : UseScaled ? 1 : 0;
|
||||
if (Addr.getExtendType() == AArch64_AM::UXTW ||
|
||||
Addr.getExtendType() == AArch64_AM::SXTW)
|
||||
Idx++;
|
||||
|
||||
int64_t ScaleFactor = 0;
|
||||
switch (VT.SimpleTy) {
|
||||
default: llvm_unreachable("Unexpected value type.");
|
||||
case MVT::i1: VTIsi1 = true; // Intentional fall-through.
|
||||
case MVT::i8: Opc = OpcTable[Idx][0]; RC = &AArch64::GPR32RegClass; break;
|
||||
case MVT::i16: Opc = OpcTable[Idx][1]; RC = &AArch64::GPR32RegClass; break;
|
||||
case MVT::i32: Opc = OpcTable[Idx][2]; RC = &AArch64::GPR32RegClass; break;
|
||||
case MVT::i64: Opc = OpcTable[Idx][3]; RC = &AArch64::GPR64RegClass; break;
|
||||
case MVT::f32: Opc = OpcTable[Idx][4]; RC = &AArch64::FPR32RegClass; break;
|
||||
case MVT::f64: Opc = OpcTable[Idx][5]; RC = &AArch64::FPR64RegClass; break;
|
||||
default:
|
||||
return false;
|
||||
case MVT::i1:
|
||||
VTIsi1 = true;
|
||||
// Intentional fall-through.
|
||||
case MVT::i8:
|
||||
Opc = UseUnscaled ? AArch64::LDURBBi : AArch64::LDRBBui;
|
||||
RC = &AArch64::GPR32RegClass;
|
||||
ScaleFactor = 1;
|
||||
break;
|
||||
case MVT::i16:
|
||||
Opc = UseUnscaled ? AArch64::LDURHHi : AArch64::LDRHHui;
|
||||
RC = &AArch64::GPR32RegClass;
|
||||
ScaleFactor = 2;
|
||||
break;
|
||||
case MVT::i32:
|
||||
Opc = UseUnscaled ? AArch64::LDURWi : AArch64::LDRWui;
|
||||
RC = &AArch64::GPR32RegClass;
|
||||
ScaleFactor = 4;
|
||||
break;
|
||||
case MVT::i64:
|
||||
Opc = UseUnscaled ? AArch64::LDURXi : AArch64::LDRXui;
|
||||
RC = &AArch64::GPR64RegClass;
|
||||
ScaleFactor = 8;
|
||||
break;
|
||||
case MVT::f32:
|
||||
Opc = UseUnscaled ? AArch64::LDURSi : AArch64::LDRSui;
|
||||
RC = TLI.getRegClassFor(VT);
|
||||
ScaleFactor = 4;
|
||||
break;
|
||||
case MVT::f64:
|
||||
Opc = UseUnscaled ? AArch64::LDURDi : AArch64::LDRDui;
|
||||
RC = TLI.getRegClassFor(VT);
|
||||
ScaleFactor = 8;
|
||||
break;
|
||||
}
|
||||
// Scale the offset.
|
||||
if (!UseUnscaled) {
|
||||
int64_t Offset = Addr.getOffset();
|
||||
if (Offset & (ScaleFactor - 1))
|
||||
// Retry using an unscaled, 9-bit, signed immediate offset.
|
||||
return EmitLoad(VT, ResultReg, Addr, MMO, /*UseUnscaled*/ true);
|
||||
|
||||
Addr.setOffset(Offset / ScaleFactor);
|
||||
}
|
||||
|
||||
// Simplify this down to something we can handle.
|
||||
if (!SimplifyAddress(Addr, VT, UseUnscaled ? 1 : ScaleFactor, UseUnscaled))
|
||||
return false;
|
||||
|
||||
// Create the base instruction, then add the operands.
|
||||
ResultReg = createResultReg(RC);
|
||||
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
||||
TII.get(Opc), ResultReg);
|
||||
AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, ScaleFactor, MMO);
|
||||
AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, MMO, UseUnscaled);
|
||||
|
||||
// Loading an i1 requires special handling.
|
||||
if (VTIsi1) {
|
||||
@ -798,8 +682,8 @@ bool AArch64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
|
||||
unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
|
||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
|
||||
ANDReg)
|
||||
.addReg(ResultReg)
|
||||
.addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
|
||||
.addReg(ResultReg)
|
||||
.addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
|
||||
ResultReg = ANDReg;
|
||||
}
|
||||
return true;
|
||||
@ -815,7 +699,7 @@ bool AArch64FastISel::SelectLoad(const Instruction *I) {
|
||||
|
||||
// See if we can handle this address.
|
||||
Address Addr;
|
||||
if (!ComputeAddress(I->getOperand(0), Addr, I->getType()))
|
||||
if (!ComputeAddress(I->getOperand(0), Addr))
|
||||
return false;
|
||||
|
||||
unsigned ResultReg;
|
||||
@ -827,63 +711,59 @@ bool AArch64FastISel::SelectLoad(const Instruction *I) {
|
||||
}
|
||||
|
||||
bool AArch64FastISel::EmitStore(MVT VT, unsigned SrcReg, Address Addr,
|
||||
MachineMemOperand *MMO) {
|
||||
// Simplify this down to something we can handle.
|
||||
if (!SimplifyAddress(Addr, VT))
|
||||
return false;
|
||||
|
||||
unsigned ScaleFactor;
|
||||
switch (VT.SimpleTy) {
|
||||
default: llvm_unreachable("Unexpected value type.");
|
||||
case MVT::i1: // fall-through
|
||||
case MVT::i8: ScaleFactor = 1; break;
|
||||
case MVT::i16: ScaleFactor = 2; break;
|
||||
case MVT::i32: // fall-through
|
||||
case MVT::f32: ScaleFactor = 4; break;
|
||||
case MVT::i64: // fall-through
|
||||
case MVT::f64: ScaleFactor = 8; break;
|
||||
}
|
||||
|
||||
MachineMemOperand *MMO, bool UseUnscaled) {
|
||||
// Negative offsets require unscaled, 9-bit, signed immediate offsets.
|
||||
// Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
|
||||
bool UseScaled = true;
|
||||
if ((Addr.getOffset() < 0) || (Addr.getOffset() & (ScaleFactor - 1))) {
|
||||
UseScaled = false;
|
||||
ScaleFactor = 1;
|
||||
}
|
||||
if (!UseUnscaled && Addr.getOffset() < 0)
|
||||
UseUnscaled = true;
|
||||
|
||||
|
||||
static const unsigned OpcTable[4][6] = {
|
||||
{ AArch64::STURBBi, AArch64::STURHHi, AArch64::STURWi, AArch64::STURXi,
|
||||
AArch64::STURSi, AArch64::STURDi },
|
||||
{ AArch64::STRBBui, AArch64::STRHHui, AArch64::STRWui, AArch64::STRXui,
|
||||
AArch64::STRSui, AArch64::STRDui },
|
||||
{ AArch64::STRBBroX, AArch64::STRHHroX, AArch64::STRWroX, AArch64::STRXroX,
|
||||
AArch64::STRSroX, AArch64::STRDroX },
|
||||
{ AArch64::STRBBroW, AArch64::STRHHroW, AArch64::STRWroW, AArch64::STRXroW,
|
||||
AArch64::STRSroW, AArch64::STRDroW }
|
||||
|
||||
};
|
||||
|
||||
unsigned Opc;
|
||||
unsigned StrOpc;
|
||||
bool VTIsi1 = false;
|
||||
bool UseRegOffset = Addr.isRegBase() && !Addr.getOffset() && Addr.getReg() &&
|
||||
Addr.getOffsetReg();
|
||||
unsigned Idx = UseRegOffset ? 2 : UseScaled ? 1 : 0;
|
||||
if (Addr.getExtendType() == AArch64_AM::UXTW ||
|
||||
Addr.getExtendType() == AArch64_AM::SXTW)
|
||||
Idx++;
|
||||
|
||||
int64_t ScaleFactor = 0;
|
||||
// Using scaled, 12-bit, unsigned immediate offsets.
|
||||
switch (VT.SimpleTy) {
|
||||
default: llvm_unreachable("Unexpected value type.");
|
||||
case MVT::i1: VTIsi1 = true;
|
||||
case MVT::i8: Opc = OpcTable[Idx][0]; break;
|
||||
case MVT::i16: Opc = OpcTable[Idx][1]; break;
|
||||
case MVT::i32: Opc = OpcTable[Idx][2]; break;
|
||||
case MVT::i64: Opc = OpcTable[Idx][3]; break;
|
||||
case MVT::f32: Opc = OpcTable[Idx][4]; break;
|
||||
case MVT::f64: Opc = OpcTable[Idx][5]; break;
|
||||
default:
|
||||
return false;
|
||||
case MVT::i1:
|
||||
VTIsi1 = true;
|
||||
case MVT::i8:
|
||||
StrOpc = UseUnscaled ? AArch64::STURBBi : AArch64::STRBBui;
|
||||
ScaleFactor = 1;
|
||||
break;
|
||||
case MVT::i16:
|
||||
StrOpc = UseUnscaled ? AArch64::STURHHi : AArch64::STRHHui;
|
||||
ScaleFactor = 2;
|
||||
break;
|
||||
case MVT::i32:
|
||||
StrOpc = UseUnscaled ? AArch64::STURWi : AArch64::STRWui;
|
||||
ScaleFactor = 4;
|
||||
break;
|
||||
case MVT::i64:
|
||||
StrOpc = UseUnscaled ? AArch64::STURXi : AArch64::STRXui;
|
||||
ScaleFactor = 8;
|
||||
break;
|
||||
case MVT::f32:
|
||||
StrOpc = UseUnscaled ? AArch64::STURSi : AArch64::STRSui;
|
||||
ScaleFactor = 4;
|
||||
break;
|
||||
case MVT::f64:
|
||||
StrOpc = UseUnscaled ? AArch64::STURDi : AArch64::STRDui;
|
||||
ScaleFactor = 8;
|
||||
break;
|
||||
}
|
||||
// Scale the offset.
|
||||
if (!UseUnscaled) {
|
||||
int64_t Offset = Addr.getOffset();
|
||||
if (Offset & (ScaleFactor - 1))
|
||||
// Retry using an unscaled, 9-bit, signed immediate offset.
|
||||
return EmitStore(VT, SrcReg, Addr, MMO, /*UseUnscaled*/ true);
|
||||
|
||||
Addr.setOffset(Offset / ScaleFactor);
|
||||
}
|
||||
|
||||
// Simplify this down to something we can handle.
|
||||
if (!SimplifyAddress(Addr, VT, UseUnscaled ? 1 : ScaleFactor, UseUnscaled))
|
||||
return false;
|
||||
|
||||
// Storing an i1 requires special handling.
|
||||
if (VTIsi1) {
|
||||
@ -891,15 +771,14 @@ bool AArch64FastISel::EmitStore(MVT VT, unsigned SrcReg, Address Addr,
|
||||
unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
|
||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
|
||||
ANDReg)
|
||||
.addReg(SrcReg)
|
||||
.addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
|
||||
.addReg(SrcReg)
|
||||
.addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
|
||||
SrcReg = ANDReg;
|
||||
}
|
||||
// Create the base instruction, then add the operands.
|
||||
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
||||
TII.get(Opc))
|
||||
.addReg(SrcReg);
|
||||
AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, ScaleFactor, MMO);
|
||||
TII.get(StrOpc)).addReg(SrcReg);
|
||||
AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, MMO, UseUnscaled);
|
||||
|
||||
return true;
|
||||
}
|
||||
@ -921,7 +800,7 @@ bool AArch64FastISel::SelectStore(const Instruction *I) {
|
||||
|
||||
// See if we can handle this address.
|
||||
Address Addr;
|
||||
if (!ComputeAddress(I->getOperand(1), Addr, I->getOperand(0)->getType()))
|
||||
if (!ComputeAddress(I->getOperand(1), Addr))
|
||||
return false;
|
||||
|
||||
if (!EmitStore(VT, SrcReg, Addr, createMachineMemOperandFor(I)))
|
||||
|
||||
@ -1,425 +0,0 @@
|
||||
; RUN: llc -mtriple=aarch64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
|
||||
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
|
||||
|
||||
; Load / Store Base Register only
|
||||
define zeroext i1 @load_breg_i1(i1* %a) {
|
||||
; CHECK-LABEL: load_breg_i1
|
||||
; CHECK: ldrb {{w[0-9]+}}, [x0]
|
||||
%1 = load i1* %a
|
||||
ret i1 %1
|
||||
}
|
||||
|
||||
define zeroext i8 @load_breg_i8(i8* %a) {
|
||||
; CHECK-LABEL: load_breg_i8
|
||||
; CHECK: ldrb {{w[0-9]+}}, [x0]
|
||||
%1 = load i8* %a
|
||||
ret i8 %1
|
||||
}
|
||||
|
||||
define zeroext i16 @load_breg_i16(i16* %a) {
|
||||
; CHECK-LABEL: load_breg_i16
|
||||
; CHECK: ldrh {{w[0-9]+}}, [x0]
|
||||
%1 = load i16* %a
|
||||
ret i16 %1
|
||||
}
|
||||
|
||||
define i32 @load_breg_i32(i32* %a) {
|
||||
; CHECK-LABEL: load_breg_i32
|
||||
; CHECK: ldr {{w[0-9]+}}, [x0]
|
||||
%1 = load i32* %a
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i64 @load_breg_i64(i64* %a) {
|
||||
; CHECK-LABEL: load_breg_i64
|
||||
; CHECK: ldr {{x[0-9]+}}, [x0]
|
||||
%1 = load i64* %a
|
||||
ret i64 %1
|
||||
}
|
||||
|
||||
define float @load_breg_f32(float* %a) {
|
||||
; CHECK-LABEL: load_breg_f32
|
||||
; CHECK: ldr {{s[0-9]+}}, [x0]
|
||||
%1 = load float* %a
|
||||
ret float %1
|
||||
}
|
||||
|
||||
define double @load_breg_f64(double* %a) {
|
||||
; CHECK-LABEL: load_breg_f64
|
||||
; CHECK: ldr {{d[0-9]+}}, [x0]
|
||||
%1 = load double* %a
|
||||
ret double %1
|
||||
}
|
||||
|
||||
define void @store_breg_i1(i1* %a) {
|
||||
; CHECK-LABEL: store_breg_i1
|
||||
; CHECK: strb {{wzr|w[0-9]+}}, [x0]
|
||||
store i1 0, i1* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_breg_i8(i8* %a) {
|
||||
; CHECK-LABEL: store_breg_i8
|
||||
; CHECK: strb wzr, [x0]
|
||||
store i8 0, i8* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_breg_i16(i16* %a) {
|
||||
; CHECK-LABEL: store_breg_i16
|
||||
; CHECK: strh wzr, [x0]
|
||||
store i16 0, i16* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_breg_i32(i32* %a) {
|
||||
; CHECK-LABEL: store_breg_i32
|
||||
; CHECK: str wzr, [x0]
|
||||
store i32 0, i32* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_breg_i64(i64* %a) {
|
||||
; CHECK-LABEL: store_breg_i64
|
||||
; CHECK: str xzr, [x0]
|
||||
store i64 0, i64* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_breg_f32(float* %a) {
|
||||
; CHECK-LABEL: store_breg_f32
|
||||
; CHECK: str {{wzr|s[0-9]+}}, [x0]
|
||||
store float 0.0, float* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_breg_f64(double* %a) {
|
||||
; CHECK-LABEL: store_breg_f64
|
||||
; CHECK: str {{xzr|d[0-9]+}}, [x0]
|
||||
store double 0.0, double* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
; Load / Store Base Register + Immediate Offset
|
||||
; Max supported negative offset
|
||||
define i32 @load_breg_immoff_1(i64 %a) {
|
||||
; CHECK-LABEL: load_breg_immoff_1
|
||||
; CHECK: ldur {{w[0-9]+}}, [x0, #-256]
|
||||
%1 = add i64 %a, -256
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
%3 = load i32* %2
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
; Min not-supported negative offset
|
||||
define i32 @load_breg_immoff_2(i64 %a) {
|
||||
; SDAG-LABEL: load_breg_immoff_2
|
||||
; SDAG: sub [[REG:x[0-9]+]], x0, #257
|
||||
; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
|
||||
; FAST-LABEL: load_breg_immoff_2
|
||||
; FAST: add [[REG:x[0-9]+]], x0, {{x[0-9]+}}
|
||||
; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
|
||||
%1 = add i64 %a, -257
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
%3 = load i32* %2
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
; Max supported unscaled offset
|
||||
define i32 @load_breg_immoff_3(i64 %a) {
|
||||
; CHECK-LABEL: load_breg_immoff_3
|
||||
; CHECK: ldur {{w[0-9]+}}, [x0, #255]
|
||||
%1 = add i64 %a, 255
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
%3 = load i32* %2
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
; Min un-supported unscaled offset
|
||||
define i32 @load_breg_immoff_4(i64 %a) {
|
||||
; SDAG-LABEL: load_breg_immoff_4
|
||||
; SDAG: add [[REG:x[0-9]+]], x0, #257
|
||||
; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
|
||||
; FAST-LABEL: load_breg_immoff_4
|
||||
; FAST: add [[REG:x[0-9]+]], x0, {{x[0-9]+}}
|
||||
; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
|
||||
%1 = add i64 %a, 257
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
%3 = load i32* %2
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
; Max supported scaled offset
|
||||
define i32 @load_breg_immoff_5(i64 %a) {
|
||||
; CHECK-LABEL: load_breg_immoff_5
|
||||
; CHECK: ldr {{w[0-9]+}}, [x0, #16380]
|
||||
%1 = add i64 %a, 16380
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
%3 = load i32* %2
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
; Min un-supported scaled offset
|
||||
define i32 @load_breg_immoff_6(i64 %a) {
|
||||
; SDAG-LABEL: load_breg_immoff_6
|
||||
; SDAG: add [[REG:x[0-9]+]], x0, #4, lsl #12
|
||||
; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
|
||||
; FAST-LABEL: load_breg_immoff_6
|
||||
; FAST: add [[REG:x[0-9]+]], x0, {{x[0-9]+}}
|
||||
; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
|
||||
%1 = add i64 %a, 16384
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
%3 = load i32* %2
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
; Max supported negative offset
|
||||
define void @store_breg_immoff_1(i64 %a) {
|
||||
; CHECK-LABEL: store_breg_immoff_1
|
||||
; CHECK: stur wzr, [x0, #-256]
|
||||
%1 = add i64 %a, -256
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
store i32 0, i32* %2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Min not-supported negative offset
|
||||
define void @store_breg_immoff_2(i64 %a) {
|
||||
; SDAG-LABEL: store_breg_immoff_2
|
||||
; SDAG: sub [[REG:x[0-9]+]], x0, #257
|
||||
; SDAG-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
|
||||
; FAST-LABEL: store_breg_immoff_2
|
||||
; FAST: add [[REG:x[0-9]+]], x0, {{x[0-9]+}}
|
||||
; FAST-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
|
||||
%1 = add i64 %a, -257
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
store i32 0, i32* %2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Max supported unscaled offset
|
||||
define void @store_breg_immoff_3(i64 %a) {
|
||||
; CHECK-LABEL: store_breg_immoff_3
|
||||
; CHECK: stur wzr, [x0, #255]
|
||||
%1 = add i64 %a, 255
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
store i32 0, i32* %2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Min un-supported unscaled offset
|
||||
define void @store_breg_immoff_4(i64 %a) {
|
||||
; SDAG-LABEL: store_breg_immoff_4
|
||||
; SDAG: add [[REG:x[0-9]+]], x0, #257
|
||||
; SDAG-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
|
||||
; FAST-LABEL: store_breg_immoff_4
|
||||
; FAST: add [[REG:x[0-9]+]], x0, {{x[0-9]+}}
|
||||
; FAST-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
|
||||
%1 = add i64 %a, 257
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
store i32 0, i32* %2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Max supported scaled offset
|
||||
define void @store_breg_immoff_5(i64 %a) {
|
||||
; CHECK-LABEL: store_breg_immoff_5
|
||||
; CHECK: str wzr, [x0, #16380]
|
||||
%1 = add i64 %a, 16380
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
store i32 0, i32* %2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Min un-supported scaled offset
|
||||
define void @store_breg_immoff_6(i64 %a) {
|
||||
; SDAG-LABEL: store_breg_immoff_6
|
||||
; SDAG: add [[REG:x[0-9]+]], x0, #4, lsl #12
|
||||
; SDAG-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
|
||||
; FAST-LABEL: store_breg_immoff_6
|
||||
; FAST: add [[REG:x[0-9]+]], x0, {{x[0-9]+}}
|
||||
; FAST-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
|
||||
%1 = add i64 %a, 16384
|
||||
%2 = inttoptr i64 %1 to i32*
|
||||
store i32 0, i32* %2
|
||||
ret void
|
||||
}
|
||||
|
||||
define i64 @load_breg_immoff_7(i64 %a) {
|
||||
; CHECK-LABEL: load_breg_immoff_7
|
||||
; CHECK: ldr {{x[0-9]+}}, [x0, #48]
|
||||
%1 = add i64 %a, 48
|
||||
%2 = inttoptr i64 %1 to i64*
|
||||
%3 = load i64* %2
|
||||
ret i64 %3
|
||||
}
|
||||
|
||||
; Flip add operands
|
||||
define i64 @load_breg_immoff_8(i64 %a) {
|
||||
; CHECK-LABEL: load_breg_immoff_8
|
||||
; CHECK: ldr {{x[0-9]+}}, [x0, #48]
|
||||
%1 = add i64 48, %a
|
||||
%2 = inttoptr i64 %1 to i64*
|
||||
%3 = load i64* %2
|
||||
ret i64 %3
|
||||
}
|
||||
|
||||
; Load Base Register + Register Offset
|
||||
define i64 @load_breg_offreg_1(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_breg_offreg_1
|
||||
; CHECK: ldr {{x[0-9]+}}, [x0, x1]
|
||||
%1 = add i64 %a, %b
|
||||
%2 = inttoptr i64 %1 to i64*
|
||||
%3 = load i64* %2
|
||||
ret i64 %3
|
||||
}
|
||||
|
||||
; Flip add operands
|
||||
define i64 @load_breg_offreg_2(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_breg_offreg_2
|
||||
; CHECK: ldr {{x[0-9]+}}, [x1, x0]
|
||||
%1 = add i64 %b, %a
|
||||
%2 = inttoptr i64 %1 to i64*
|
||||
%3 = load i64* %2
|
||||
ret i64 %3
|
||||
}
|
||||
|
||||
; Load Base Register + Register Offset + Immediate Offset
|
||||
define i64 @load_breg_offreg_immoff_1(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_breg_offreg_immoff_1
|
||||
; CHECK: add [[REG:x[0-9]+]], x0, x1
|
||||
; CHECK-NEXT: ldr x0, {{\[}}[[REG]], #48{{\]}}
|
||||
%1 = add i64 %a, %b
|
||||
%2 = add i64 %1, 48
|
||||
%3 = inttoptr i64 %2 to i64*
|
||||
%4 = load i64* %3
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
define i64 @load_breg_offreg_immoff_2(i64 %a, i64 %b) {
|
||||
; SDAG-LABEL: load_breg_offreg_immoff_2
|
||||
; SDAG: add [[REG1:x[0-9]+]], x0, x1
|
||||
; SDAG-NEXT: add [[REG2:x[0-9]+]], [[REG1]], #15, lsl #12
|
||||
; SDAG-NEXT: ldr x0, {{\[}}[[REG2]]{{\]}}
|
||||
; FAST-LABEL: load_breg_offreg_immoff_2
|
||||
; FAST: add [[REG:x[0-9]+]], x0, {{x[0-9]+}}
|
||||
; FAST-NEXT: ldr x0, {{\[}}[[REG]], x1{{\]}}
|
||||
%1 = add i64 %a, %b
|
||||
%2 = add i64 %1, 61440
|
||||
%3 = inttoptr i64 %2 to i64*
|
||||
%4 = load i64* %3
|
||||
ret i64 %4
|
||||
}
|
||||
|
||||
; Load Base Register + Scaled Register Offset
|
||||
define i32 @load_breg_shift_offreg_1(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_breg_shift_offreg_1
|
||||
; CHECK: ldr {{w[0-9]+}}, [x1, x0, lsl #2]
|
||||
%1 = shl i64 %a, 2
|
||||
%2 = add i64 %1, %b
|
||||
%3 = inttoptr i64 %2 to i32*
|
||||
%4 = load i32* %3
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i32 @load_breg_shift_offreg_2(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_breg_shift_offreg_2
|
||||
; CHECK: ldr {{w[0-9]+}}, [x1, x0, lsl #2]
|
||||
%1 = shl i64 %a, 2
|
||||
%2 = add i64 %b, %1
|
||||
%3 = inttoptr i64 %2 to i32*
|
||||
%4 = load i32* %3
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define i32 @load_breg_shift_offreg_3(i64 %a, i64 %b) {
|
||||
; SDAG-LABEL: load_breg_shift_offreg_3
|
||||
; SDAG: lsl [[REG:x[0-9]+]], x0, #2
|
||||
; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x1, lsl #2{{\]}}
|
||||
; FAST-LABEL: load_breg_shift_offreg_3
|
||||
; FAST: lsl [[REG:x[0-9]+]], x1, {{x[0-9]+}}
|
||||
; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
|
||||
%1 = shl i64 %a, 2
|
||||
%2 = shl i64 %b, 2
|
||||
%3 = add i64 %1, %2
|
||||
%4 = inttoptr i64 %3 to i32*
|
||||
%5 = load i32* %4
|
||||
ret i32 %5
|
||||
}
|
||||
|
||||
define i32 @load_breg_shift_offreg_4(i64 %a, i64 %b) {
|
||||
; SDAG-LABEL: load_breg_shift_offreg_4
|
||||
; SDAG: lsl [[REG:x[0-9]+]], x1, #2
|
||||
; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
|
||||
; FAST-LABEL: load_breg_shift_offreg_4
|
||||
; FAST: lsl [[REG:x[0-9]+]], x0, {{x[0-9]+}}
|
||||
; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x1, lsl #2{{\]}}
|
||||
%1 = shl i64 %a, 2
|
||||
%2 = shl i64 %b, 2
|
||||
%3 = add i64 %2, %1
|
||||
%4 = inttoptr i64 %3 to i32*
|
||||
%5 = load i32* %4
|
||||
ret i32 %5
|
||||
}
|
||||
|
||||
define i32 @load_breg_shift_offreg_5(i64 %a, i64 %b) {
|
||||
; SDAG-LABEL: load_breg_shift_offreg_5
|
||||
; SDAG: lsl [[REG:x[0-9]+]], x1, #3
|
||||
; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
|
||||
; FAST-LABEL: load_breg_shift_offreg_5
|
||||
; FAST: lsl [[REG:x[0-9]+]], x1, {{x[0-9]+}}
|
||||
; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
|
||||
%1 = shl i64 %a, 2
|
||||
%2 = shl i64 %b, 3
|
||||
%3 = add i64 %1, %2
|
||||
%4 = inttoptr i64 %3 to i32*
|
||||
%5 = load i32* %4
|
||||
ret i32 %5
|
||||
}
|
||||
|
||||
|
||||
; Load Base Register + Scaled Register Offset + Sign/Zero extension
|
||||
define i32 @load_breg_zext_shift_offreg_1(i32 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_breg_zext_shift_offreg_1
|
||||
; CHECK: ldr {{w[0-9]+}}, [x1, w0, uxtw #2]
|
||||
%1 = zext i32 %a to i64
|
||||
%2 = shl i64 %1, 2
|
||||
%3 = add i64 %2, %b
|
||||
%4 = inttoptr i64 %3 to i32*
|
||||
%5 = load i32* %4
|
||||
ret i32 %5
|
||||
}
|
||||
|
||||
define i32 @load_breg_zext_shift_offreg_2(i32 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_breg_zext_shift_offreg_2
|
||||
; CHECK: ldr {{w[0-9]+}}, [x1, w0, uxtw #2]
|
||||
%1 = zext i32 %a to i64
|
||||
%2 = shl i64 %1, 2
|
||||
%3 = add i64 %b, %2
|
||||
%4 = inttoptr i64 %3 to i32*
|
||||
%5 = load i32* %4
|
||||
ret i32 %5
|
||||
}
|
||||
|
||||
define i32 @load_breg_sext_shift_offreg_1(i32 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_breg_sext_shift_offreg_1
|
||||
; CHECK: ldr {{w[0-9]+}}, [x1, w0, sxtw #2]
|
||||
%1 = sext i32 %a to i64
|
||||
%2 = shl i64 %1, 2
|
||||
%3 = add i64 %2, %b
|
||||
%4 = inttoptr i64 %3 to i32*
|
||||
%5 = load i32* %4
|
||||
ret i32 %5
|
||||
}
|
||||
|
||||
define i32 @load_breg_sext_shift_offreg_2(i32 %a, i64 %b) {
|
||||
; CHECK-LABEL: load_breg_sext_shift_offreg_2
|
||||
; CHECK: ldr {{w[0-9]+}}, [x1, w0, sxtw #2]
|
||||
%1 = sext i32 %a to i64
|
||||
%2 = shl i64 %1, 2
|
||||
%3 = add i64 %b, %2
|
||||
%4 = inttoptr i64 %3 to i32*
|
||||
%5 = load i32* %4
|
||||
ret i32 %5
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user