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Fix FastISel's assumption that i1 values are always zero-extended

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by inserting explicit zero extensions where necessary. Included
is a testcase where SelectionDAG produces a virtual register
holding an i1 value which FastISel previously mistakenly assumed
to be zero-extended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66941 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-03-13 20:42:20 +00:00
parent 7150371097
commit 14ea1ec232
4 changed files with 42 additions and 3 deletions
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5
include/llvm/CodeGen/FastISel.h
View File

@ -269,6 +269,11 @@ protected:
unsigned FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
unsigned Op0, uint32_t Idx);
/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
/// with all but the least significant bit set to zero.
unsigned FastEmitZExtFromI1(MVT::SimpleValueType VT,
unsigned Op);
/// FastEmitBranch - Emit an unconditional branch to the given block,
/// unless it is the immediate (fall-through) successor, and update
/// the CFG.

15
lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@ -497,7 +497,14 @@ bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
if (!InputReg)
// Unhandled operand. Halt "fast" selection and bail.
return false;
// If the operand is i1, arrange for the high bits in the register to be zero.
if (I->getOperand(0)->getType() == Type::Int1Ty) {
InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
if (!InputReg)
return false;
}
unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
DstVT.getSimpleVT(),
Opcode,
@ -970,3 +977,9 @@ unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
}
return ResultReg;
}
/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
/// with all but the least significant bit set to zero.
unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) {
return FastEmit_ri(VT, VT, ISD::AND, Op, 1);
}

6
lib/Target/X86/X86FastISel.cpp
View File

@ -671,12 +671,14 @@ bool X86FastISel::X86SelectCmp(Instruction *I) {
}
bool X86FastISel::X86SelectZExt(Instruction *I) {
// Special-case hack: The only i1 values we know how to produce currently
// set the upper bits of an i8 value to zero.
// Handle zero-extension from i1 to i8, which is common.
if (I->getType() == Type::Int8Ty &&
I->getOperand(0)->getType() == Type::Int1Ty) {
unsigned ResultReg = getRegForValue(I->getOperand(0));
if (ResultReg == 0) return false;
// Set the high bits to zero.
ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg);
if (ResultReg == 0) return false;
UpdateValueMap(I, ResultReg);
return true;
}

19
test/CodeGen/X86/fast-isel-i1.ll Normal file
View File

@ -0,0 +1,19 @@
; RUN: llvm-as < %s | llc -march=x86 -fast-isel | grep {andb \$1, %}
declare i64 @bar(i64)
define i32 @foo(i64 %x) nounwind {
%y = add i64 %x, -3 ; <i64> [#uses=1]
%t = call i64 @bar(i64 %y) ; <i64> [#uses=1]
%s = mul i64 %t, 77 ; <i64> [#uses=1]
%z = trunc i64 %s to i1 ; <i1> [#uses=1]
br label %next
next: ; preds = %0
%u = zext i1 %z to i32 ; <i32> [#uses=1]
%v = add i32 %u, 1999 ; <i32> [#uses=1]
br label %exit
exit: ; preds = %next
ret i32 %v
}