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Fix FastISel's assumption that i1 values are always zero-extended
by inserting explicit zero extensions where necessary. Included is a testcase where SelectionDAG produces a virtual register holding an i1 value which FastISel previously mistakenly assumed to be zero-extended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66941 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -269,6 +269,11 @@ protected:
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unsigned FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
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unsigned FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
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unsigned Op0, uint32_t Idx);
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unsigned Op0, uint32_t Idx);
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/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
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/// with all but the least significant bit set to zero.
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unsigned FastEmitZExtFromI1(MVT::SimpleValueType VT,
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unsigned Op);
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/// FastEmitBranch - Emit an unconditional branch to the given block,
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/// FastEmitBranch - Emit an unconditional branch to the given block,
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/// unless it is the immediate (fall-through) successor, and update
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/// unless it is the immediate (fall-through) successor, and update
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/// the CFG.
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/// the CFG.
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@ -498,6 +498,13 @@ bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
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// Unhandled operand. Halt "fast" selection and bail.
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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return false;
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// If the operand is i1, arrange for the high bits in the register to be zero.
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if (I->getOperand(0)->getType() == Type::Int1Ty) {
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InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
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if (!InputReg)
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return false;
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}
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unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
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unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
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DstVT.getSimpleVT(),
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DstVT.getSimpleVT(),
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Opcode,
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Opcode,
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@ -970,3 +977,9 @@ unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
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}
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}
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return ResultReg;
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return ResultReg;
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}
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}
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/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
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/// with all but the least significant bit set to zero.
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unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) {
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return FastEmit_ri(VT, VT, ISD::AND, Op, 1);
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}
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@ -671,12 +671,14 @@ bool X86FastISel::X86SelectCmp(Instruction *I) {
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}
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}
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bool X86FastISel::X86SelectZExt(Instruction *I) {
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bool X86FastISel::X86SelectZExt(Instruction *I) {
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// Special-case hack: The only i1 values we know how to produce currently
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// Handle zero-extension from i1 to i8, which is common.
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// set the upper bits of an i8 value to zero.
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if (I->getType() == Type::Int8Ty &&
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if (I->getType() == Type::Int8Ty &&
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I->getOperand(0)->getType() == Type::Int1Ty) {
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I->getOperand(0)->getType() == Type::Int1Ty) {
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unsigned ResultReg = getRegForValue(I->getOperand(0));
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unsigned ResultReg = getRegForValue(I->getOperand(0));
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if (ResultReg == 0) return false;
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if (ResultReg == 0) return false;
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// Set the high bits to zero.
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ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg);
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if (ResultReg == 0) return false;
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UpdateValueMap(I, ResultReg);
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UpdateValueMap(I, ResultReg);
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return true;
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return true;
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}
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}
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19
test/CodeGen/X86/fast-isel-i1.ll
Normal file
19
test/CodeGen/X86/fast-isel-i1.ll
Normal file
@ -0,0 +1,19 @@
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; RUN: llvm-as < %s | llc -march=x86 -fast-isel | grep {andb \$1, %}
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declare i64 @bar(i64)
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define i32 @foo(i64 %x) nounwind {
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%y = add i64 %x, -3 ; <i64> [#uses=1]
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%t = call i64 @bar(i64 %y) ; <i64> [#uses=1]
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%s = mul i64 %t, 77 ; <i64> [#uses=1]
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%z = trunc i64 %s to i1 ; <i1> [#uses=1]
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br label %next
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next: ; preds = %0
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%u = zext i1 %z to i32 ; <i32> [#uses=1]
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%v = add i32 %u, 1999 ; <i32> [#uses=1]
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br label %exit
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exit: ; preds = %next
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ret i32 %v
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}
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