diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td
index bbd8c92720d..527e8b5a6ab 100644
--- a/lib/Target/ARM/ARMRegisterInfo.td
+++ b/lib/Target/ARM/ARMRegisterInfo.td
@@ -309,7 +309,8 @@ def TuplesOE2D : RegisterTuples<[dsub_0, dsub_1],
 
 // Register class representing a pair of consecutive D registers.
 // Use the Q registers for the even-odd pairs.
-def DPair : RegisterClass<"ARM", [v2i64], 128, (interleave QPR, TuplesOE2D)> {
+def DPair : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
+                          128, (interleave QPR, TuplesOE2D)> {
   // Allocate starting at non-VFP2 registers D16-D31 first.
   let AltOrders = [(rotl DPair, 16)];
   let AltOrderSelect = [{ return 1; }];