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add all supported formats to the vector register file

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27115 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-03-25 07:36:56 +00:00
parent 5814c20766
commit 150ffa7842
1 changed files with 1 additions and 1 deletions
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lib/Target/PowerPC/PPCRegisterInfo.td
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@ -259,7 +259,7 @@ def F4RC : RegisterClass<"PPC", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7,
F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
def VRRC : RegisterClass<"PPC", [v16i8,v4f32,v4i32], 128,
def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
[V0, V1, V2, V3, V4, V5,
V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21,
V22, V23, V24, V25, V26, V27, V28, V29, V30, V31]>;