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https://github.com/c64scene-ar/llvm-6502.git
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Adds support for variable sized allocas. For a variable sized alloca,
code is inserted to first check if the current stacklet has enough space. If so, space is allocated by simply decrementing the stack pointer. Otherwise a runtime routine (__morestack_allocate_stack_space in libgcc) is called which allocates the required memory from the heap. Patch by Sanjoy Das. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138818 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -51,6 +51,7 @@
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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using namespace dwarf;
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@ -522,8 +523,9 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC,
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(Subtarget->is64Bit() ? MVT::i64 : MVT::i32),
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(Subtarget->isTargetCOFF()
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&& !Subtarget->isTargetEnvMacho()
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((Subtarget->isTargetCOFF()
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&& !Subtarget->isTargetEnvMacho()) ||
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EnableSegmentedStacks
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? Custom : Expand));
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if (!UseSoftFloat && X86ScalarSSEf64) {
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@ -8844,8 +8846,10 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
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SDValue
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X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
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SelectionDAG &DAG) const {
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assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) &&
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"This should be used only on Windows targets");
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assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
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EnableSegmentedStacks) &&
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"This should be used only on Windows targets or when segmented stacks "
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"are being used.");
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assert(!Subtarget->isTargetEnvMacho());
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DebugLoc dl = Op.getDebugLoc();
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@ -8854,23 +8858,49 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
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SDValue Size = Op.getOperand(1);
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// FIXME: Ensure alignment here
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SDValue Flag;
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bool Is64Bit = Subtarget->is64Bit();
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EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
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EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
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unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
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if (EnableSegmentedStacks) {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
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Flag = Chain.getValue(1);
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if (Is64Bit) {
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// The 64 bit implementation of segmented stacks needs to clobber both r10
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// r11. This makes it impossible to use it along with nested paramenters.
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const Function *F = MF.getFunction();
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
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for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
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I != E; I++)
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if (I->hasNestAttr())
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report_fatal_error("Cannot use segmented stacks with functions that "
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"have nested arguments.");
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}
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Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
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Flag = Chain.getValue(1);
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const TargetRegisterClass *AddrRegClass =
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getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
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unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
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Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
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SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
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DAG.getRegister(Vreg, SPTy));
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SDValue Ops1[2] = { Value, Chain };
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return DAG.getMergeValues(Ops1, 2, dl);
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} else {
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SDValue Flag;
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unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
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Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
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Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
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Flag = Chain.getValue(1);
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
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SDValue Ops1[2] = { Chain.getValue(0), Chain };
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return DAG.getMergeValues(Ops1, 2, dl);
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Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
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Flag = Chain.getValue(1);
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Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
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SDValue Ops1[2] = { Chain.getValue(0), Chain };
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return DAG.getMergeValues(Ops1, 2, dl);
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}
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}
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SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
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@ -11634,6 +11664,119 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
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return sinkMBB;
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}
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MachineBasicBlock *
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X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
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bool Is64Bit) const {
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc DL = MI->getDebugLoc();
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MachineFunction *MF = BB->getParent();
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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assert(EnableSegmentedStacks);
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unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
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unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
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// BB:
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// ... [Till the alloca]
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// If stacklet is not large enough, jump to mallocMBB
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//
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// bumpMBB:
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// Allocate by subtracting from RSP
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// Jump to continueMBB
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//
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// mallocMBB:
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// Allocate by call to runtime
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//
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// continueMBB:
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// ...
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// [rest of original BB]
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//
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MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineRegisterInfo &MRI = MF->getRegInfo();
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const TargetRegisterClass *AddrRegClass =
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getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
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unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
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bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
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tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
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sizeVReg = MI->getOperand(1).getReg(),
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physSPReg = Is64Bit ? X86::RSP : X86::ESP;
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MachineFunction::iterator MBBIter = BB;
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++MBBIter;
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MF->insert(MBBIter, bumpMBB);
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MF->insert(MBBIter, mallocMBB);
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MF->insert(MBBIter, continueMBB);
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continueMBB->splice(continueMBB->begin(), BB, llvm::next
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(MachineBasicBlock::iterator(MI)), BB->end());
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continueMBB->transferSuccessorsAndUpdatePHIs(BB);
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// Add code to the main basic block to check if the stack limit has been hit,
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// and if so, jump to mallocMBB otherwise to bumpMBB.
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BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
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BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), tmpSPVReg)
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.addReg(tmpSPVReg).addReg(sizeVReg);
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BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
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.addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg)
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.addReg(tmpSPVReg);
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BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
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// bumpMBB simply decreases the stack pointer, since we know the current
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// stacklet has enough space.
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BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
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.addReg(tmpSPVReg);
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BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
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.addReg(tmpSPVReg);
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BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
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// Calls into a routine in libgcc to allocate more space from the heap.
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if (Is64Bit) {
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BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
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.addReg(sizeVReg);
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BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
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.addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI);
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} else {
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BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
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.addImm(12);
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BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
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BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
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.addExternalSymbol("__morestack_allocate_stack_space");
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}
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if (!Is64Bit)
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BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
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.addImm(16);
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BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
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.addReg(Is64Bit ? X86::RAX : X86::EAX);
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BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
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// Set up the CFG correctly.
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BB->addSuccessor(bumpMBB);
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BB->addSuccessor(mallocMBB);
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mallocMBB->addSuccessor(continueMBB);
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bumpMBB->addSuccessor(continueMBB);
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// Take care of the PHI nodes.
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BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
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MI->getOperand(0).getReg())
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.addReg(mallocPtrVReg).addMBB(mallocMBB)
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.addReg(bumpSPPtrVReg).addMBB(bumpMBB);
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// Delete the original pseudo instruction.
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MI->eraseFromParent();
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// And we're done.
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return continueMBB;
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}
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MachineBasicBlock *
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X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
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MachineBasicBlock *BB) const {
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@ -11769,6 +11912,10 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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return BB;
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case X86::WIN_ALLOCA:
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return EmitLoweredWinAlloca(MI, BB);
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case X86::SEG_ALLOCA_32:
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return EmitLoweredSegAlloca(MI, BB, false);
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case X86::SEG_ALLOCA_64:
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return EmitLoweredSegAlloca(MI, BB, true);
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case X86::TLSCall_32:
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case X86::TLSCall_64:
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return EmitLoweredTLSCall(MI, BB);
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@ -942,6 +942,10 @@ namespace llvm {
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MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
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MachineBasicBlock *BB,
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bool Is64Bit) const;
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MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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