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https://github.com/c64scene-ar/llvm-6502.git
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Don't force promotion of return arguments on the callee.
Some architectures (like x86) don't require it. This fixes bug 3779. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67132 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -979,15 +979,6 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
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for (unsigned j = 0, f = NumValues; j != f; ++j) {
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MVT VT = ValueVTs[j];
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// FIXME: C calling convention requires the return type to be promoted to
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// at least 32-bit. But this is not necessary for non-C calling
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// conventions.
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if (VT.isInteger()) {
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MVT MinVT = TLI.getRegisterType(MVT::i32);
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if (VT.bitsLT(MinVT))
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VT = MinVT;
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}
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unsigned NumParts = TLI.getNumRegisters(VT);
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MVT PartVT = TLI.getRegisterType(VT);
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SmallVector<SDValue, 4> Parts(NumParts);
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@ -1,7 +1,7 @@
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; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep and %t1.s | count 234
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; RUN: grep and %t1.s | count 230
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; RUN: grep andc %t1.s | count 85
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; RUN: grep andi %t1.s | count 37
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; RUN: grep andi %t1.s | count 35
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; RUN: grep andhi %t1.s | count 30
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; RUN: grep andbi %t1.s | count 4
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@ -1,8 +1,5 @@
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; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep eqv %t1.s | count 18
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; RUN: grep xshw %t1.s | count 6
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; RUN: grep xsbh %t1.s | count 3
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; RUN: grep andi %t1.s | count 3
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; Test the 'eqv' instruction, whose boolean expression is:
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; (a & b) | (~a & ~b), which simplifies to
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@ -1,5 +1,5 @@
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; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep ilh %t1.s | count 5
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; RUN: grep ilh %t1.s | count 15
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; RUN: grep ceqh %t1.s | count 29
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; RUN: grep ceqhi %t1.s | count 13
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; RUN: grep clgth %t1.s | count 15
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@ -1,5 +1,5 @@
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; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep "ilh" %t1.s | count 5
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; RUN: grep "ilh" %t1.s | count 11
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
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target triple = "spu"
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@ -1,8 +1,6 @@
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; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep nand %t1.s | count 90
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; RUN: grep and %t1.s | count 94
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; RUN: grep xsbh %t1.s | count 2
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; RUN: grep xshw %t1.s | count 4
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; RUN: grep and %t1.s | count 90
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
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target triple = "spu"
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@ -1,5 +1,4 @@
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; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep and %t1.s | count 2
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; RUN: grep orc %t1.s | count 85
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; RUN: grep ori %t1.s | count 30
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; RUN: grep orhi %t1.s | count 30
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@ -3,8 +3,6 @@
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; RUN: grep {shlhi } %t1.s | count 3
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; RUN: grep {shl } %t1.s | count 9
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; RUN: grep {shli } %t1.s | count 3
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; RUN: grep {xshw } %t1.s | count 5
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; RUN: grep {and } %t1.s | count 5
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; RUN: grep {andi } %t1.s | count 2
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; RUN: grep {rotmi } %t1.s | count 2
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; RUN: grep {rotqmbyi } %t1.s | count 1
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@ -6,13 +6,13 @@
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; RUN: grep 771 %t1.s | count 4
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; RUN: grep 515 %t1.s | count 2
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; RUN: grep 1799 %t1.s | count 2
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; RUN: grep 1543 %t1.s | count 5
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; RUN: grep 1029 %t1.s | count 3
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; RUN: grep 1543 %t1.s | count 3
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; RUN: grep 1029 %t1.s | count 1
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; RUN: grep {shli.*, 4} %t1.s | count 4
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; RUN: grep stqx %t1.s | count 4
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; RUN: grep ilhu %t1.s | count 11
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; RUN: grep iohl %t1.s | count 8
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; RUN: grep shufb %t1.s | count 15
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; RUN: grep ilhu %t1.s | count 9
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; RUN: grep iohl %t1.s | count 6
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; RUN: grep shufb %t1.s | count 13
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; RUN: grep frds %t1.s | count 1
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; ModuleID = 'stores.bc'
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@ -3,8 +3,6 @@
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; RUN: grep lqa %t1.s | count 5
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; RUN: grep lqd %t1.s | count 11
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; RUN: grep rotqbyi %t1.s | count 7
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; RUN: grep xshw %t1.s | count 1
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; RUN: grep andi %t1.s | count 5
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; RUN: grep cbd %t1.s | count 3
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; RUN: grep chd %t1.s | count 1
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; RUN: grep cwd %t1.s | count 3
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@ -14,8 +12,6 @@
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; RUN: grep ilhu %t2.s | count 16
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; RUN: grep lqd %t2.s | count 16
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; RUN: grep rotqbyi %t2.s | count 7
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; RUN: grep xshw %t2.s | count 1
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; RUN: grep andi %t2.s | count 5
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; RUN: grep cbd %t2.s | count 3
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; RUN: grep chd %t2.s | count 1
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; RUN: grep cwd %t2.s | count 3
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@ -1,4 +1,4 @@
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; RUN: llvm-as < %s | llc -march=x86 | grep {movsbl}
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; RUN: llvm-as < %s | llc -march=x86 | not grep {movsbl}
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@X = global i32 0 ; <i32*> [#uses=1]
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test/CodeGen/X86/20090313-signext.ll
Normal file
18
test/CodeGen/X86/20090313-signext.ll
Normal file
@ -0,0 +1,18 @@
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; RUN: llvm-as < %s | llc -march=x86-64 > %t
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; RUN: grep {movswl %ax, %edi} %t
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; RUN: grep {movw x(%rip), %ax} %t
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@x = common global i16 0
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define signext i16 @f() nounwind {
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entry:
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%0 = tail call signext i16 @h() nounwind
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%1 = sext i16 %0 to i32
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tail call void @g(i32 %1) nounwind
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%2 = load i16* @x, align 2
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ret i16 %2
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}
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declare signext i16 @h()
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declare void @g(i32)
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@ -10,7 +10,7 @@ entry:
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ret float %iftmp.0.0
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}
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; RUN: llvm-as < %s | llc | grep {movsbl.*(%e.x,%e.x,4), %eax}
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; RUN: llvm-as < %s | llc | grep {movb.*(%e.x,%e.x,4), %al}
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define signext i8 @test(i8* nocapture %P, double %F) nounwind readonly {
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entry:
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%0 = fcmp olt double %F, 4.200000e+01 ; <i1> [#uses=1]
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@ -1,5 +1,6 @@
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; RUN: llvm-as < %s | llc -march=x86 | grep {movzbl.7(%...)}
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; RUN: llvm-as < %s | llc -march=x86 | not grep leal
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; RUN: llvm-as < %s | llc -march=x86 > %t
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; RUN: grep {movb.7(%...)} %t
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; RUN: not grep leal %t
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define i8 @test(i32 *%P) nounwind {
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%Q = getelementptr i32* %P, i32 1
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@ -1,5 +1,6 @@
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; RUN: llvm-as < %s | llc -march=x86 > %t
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; RUN: grep movsbl %t
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; RUN: grep movb %t
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; RUN: not grep movsbl %t
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; RUN: not grep movz %t
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; RUN: not grep and %t
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@ -1,5 +1,5 @@
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; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
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; RUN: grep {movzwl %gs:i@NTPOFF, %eax} %t
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; RUN: grep {movw %gs:i@NTPOFF, %ax} %t
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@i = thread_local global i16 15
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@ -1,5 +1,5 @@
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; RUN: llvm-as < %s | llc -march=x86 -mtriple=i386-linux-gnu > %t
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; RUN: grep {movzbl %gs:i@NTPOFF, %eax} %t
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; RUN: grep {movb %gs:i@NTPOFF, %al} %t
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@i = thread_local global i8 15
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