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Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135722 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -623,9 +623,10 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
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MISC("t_bltarget", "kOperandTypeARMBranchTarget"); // ?
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MISC("t_blxtarget", "kOperandTypeARMBranchTarget"); // ?
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MISC("so_reg_imm", "kOperandTypeARMSoReg"); // R, R, I
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MISC("so_reg_reg", "kOperandTypeARMSoReg"); // R, R, I
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MISC("shift_so_reg", "kOperandTypeARMSoReg"); // R, R, I
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MISC("so_reg_imm", "kOperandTypeARMSoRegReg"); // R, R, I
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MISC("so_reg_reg", "kOperandTypeARMSoRegImm"); // R, R, I
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MISC("shift_so_reg_reg", "kOperandTypeARMSoRegReg"); // R, R, I
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MISC("shift_so_reg_imm", "kOperandTypeARMSoRegImm"); // R, R, I
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MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I
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MISC("so_imm", "kOperandTypeARMSoImm"); // I
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MISC("rot_imm", "kOperandTypeARMRotImm"); // I
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@@ -854,7 +855,8 @@ static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
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operandTypes.addEntry("kOperandTypeX86EffectiveAddress");
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operandTypes.addEntry("kOperandTypeX86PCRelative");
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operandTypes.addEntry("kOperandTypeARMBranchTarget");
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operandTypes.addEntry("kOperandTypeARMSoReg");
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operandTypes.addEntry("kOperandTypeARMSoRegReg");
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operandTypes.addEntry("kOperandTypeARMSoRegImm");
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operandTypes.addEntry("kOperandTypeARMSoImm");
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operandTypes.addEntry("kOperandTypeARMRotImm");
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operandTypes.addEntry("kOperandTypeARMSoImm2Part");
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